Convert Leds to 7 Segment Display - Page 2 - Electronic Circuits Projects Diagrams Free

Sebi · 14th August 2003, 07:22 AM

Yes, ofcourse.In this case no need the pull-down resistors, but the inverter inputs need pull-up resistors.

**mechie** · 14th August 2003, 01:52 PM

Sebi
Sorry if I seem to be picking on you but -
that last circuit of yours with the NAND gates has a flaw...
If input '3' is high (active) then the NAND will block input '2' - Great! but...
As input '2' is now blocked there is nothing to stop input '1' from sneaking through ...
so the 7-seg display still shows an '8' lit up ('1' & '3' superimposed).

If I steal your circuit and add some diode 'AND' gates and add the input inverters aleady mentioned ...

I still think the Bogdanfirst's circuit using two ICs (plus input inverters) is a little more compact even if it is nowhere near as much fun :wink:

laroche73 · 19th August 2003, 06:09 AM

bogdanfirst had a good solution (e said the same thing in schematic form), and it's probably the quickest to implement when design time is considered. The package count is 3 IC's, with the inverters. Sebi's idea also does the job, with 6 NAND gates, 6 inverters, and 41(!) diodes (as mechie pointed out). Note that the priority encoder w/BCD to 7segment decoder will display a "0" when none of the comparators are on, while the "diode ROM" will blank the display.

Here's another way to approach the problem. It doesn't require any diodes or MSI parts, just eight 2-input gates, for a total package count of two ICs. (btw, this would make a good test question for an introductory course in digital electronics)

Partial decoding of the inputs can produce the required outputs, since there are many "don't care" states (57 out of 64). In general, the more "don't care" states there are, the better the decoding logic can be minimized (where the "don't care states" are located in the karnaugh map is also important).

Starting with the truth table:

Code:

       LED                    Segment
       ---                    -------

 L1 L2 L3 L4 L5 L6         A B C D E F G    Display
 -- -- -- -- -- --         - - - - - - -    -------
 1  1  1  1  1  1          0 0 0 0 0 0 1      "0"
 0  1  1  1  1  1          1 0 0 1 1 1 1      "1"
 0  0  1  1  1  1          0 0 1 0 0 1 0      "2"
 0  0  0  1  1  1          0 0 0 0 1 1 0      "3"
 0  0  0  0  1  1          1 0 0 1 1 0 0      "4"
 0  0  0  0  0  1          0 1 0 0 1 0 0      "5"
 0  0  0  0  0  0          0 1 0 0 0 0 0      "6"

The simplest case is segment "G". From inspection, "G" is identical to L2, so no logic is required. Likewise, segment "B" is the inverse of L5. Decoding the other segments is only slightly more complicated...

Example: "F" is the same as L4, except at digit "0". A high on L1 or a low on L4 should drive the segment low.

So, segment "F" = (L1 + L4')' => (L1' * L4), using demorgan's theorem.

A similar approach to decoding the other segments yields:

Segment "G" = L2

Segment "F" = (L1' * L4)

Segment "E" = (L1' * L2) + (L3' * L6)

Segment "D", "A" = (L1' * L2) + (L4' * L5)

Segment "C" = (L2' * L3)

Segment "B" = L5'

This looks pretty simple, and as it stands would take 9 gates to implement; 8 two-input gates and 1 inverter ("D" and "E" can share the L1' * L2 term, and "G" doesn't need any logic). The only problem is that most of the gates are of type "AND with one inverted input (AND2N1)". OK if you're implementing the decode logic within a PLD or FPGA, but standard TTL and CMOS families don't offer this type of gate as a primitive. To build the logic using standard SSI parts would require 5 AND gates, 2 OR gates, and 6 inverters.

Even using three SSI packages (74xx08, 74xx02, 74xx14, for example) and the fact that a NOR gate is equivalent to a negative logic AND, you'd still be one inverter short.

We can minimize the logic for a better fit with standard ICs by noting that a XOR gate implements the function (L1' * L2) + (L1 * L2'). Since the second term always falls under one of the "don't care" states in this truth table, XOR gates can substitute for the AND2N1 gates throughout the decoding logic. XOR gates can also replace the two OR gates, for the same reason. Finally, if a XOR gate is used to implement the inverter (by tying one of the inputs to VCC), we end up with a grand total of 8 XOR gates, or two SSI packages (74xx86 or CD4070). Not bad. 8)

The new equations using XOR gates are:

Segment "G" = L2

Segment "F" = L1 @ L4

Segment "E" = L1 @ L2 @ L3 @ L6

Segment "D", "A" = L1 @ L2 @ L4 @ L5

Segment "C" = L2 @ L3

Segment "B" = L5 @ Vcc

(Lacking a simulator at the moment, I tested this circuit on a breadboard to check my logic and it works as advertised)

The logic assumes a common-anode seven segment display, similar to the original LED setup. To make the display brightness more consistent across digits, a current limiting resistor should be used for each
segment, rather than having just one at the display's anode.

Of course, a simple PAL like the 16V8 could do the job in one package, but where's the fun in that?

- CAL

http://www.tinaja.com/glib/elesimp.pdf
--------------

Note 1:

In the original design no LEDs are on when all of the comparators are off. If you allow the same for the 7-segment display (blank instead of "0") one more gate can be eliminated, but the IC package count remains the same.

The equations become:

Segment "G" = L2

Segment "F" = L4

Segment "E" = (L2 @ L3) @ L6

Segment "D","A" = L4 @ L5 @ L2

Segment "C" = L1 @ (L2 @ L3)

Segment "B" = L1 @ (L5 @ Vcc) -- (XNOR function)

Segments "C" and "E" share the (L2 @ L3) term.
As before, XOR gates are used to minimize the package count.

Note 2:

Another minor point to keep in mind; the SN7445 and CD4511 BCD-seven segment decoder ICs do not output a "tail" on digits 6 (seg "A") and 9 (seg "D"). Most modern displays do (check your VCR or digital clock) and people seem to prefer this. It takes additional logic to add on the "tails" when using these decoder ICs.

laroche73 · 19th August 2003, 06:16 AM

Sorry about the truth table display in the preceeding post, the spaces got squished out. It's the same as the one on the schematic, and it's more readable there.

czxjuren · 19th August 2003, 07:17 AM

i think that should add one led

**mechie** · 19th August 2003, 04:46 PM

laroche73
I took the liberty of a MOD-EDIT on you excellent posting simply to correct the truth table layout.
It displays correctly (monospaced font) if you surround such things with the {code} and {/code} markers (note curly brackets to avoid triggering that mode here !).

laroche73 · 19th August 2003, 08:53 PM

Thanks for correcting my truth table, mechie. Not only were the spaces squished out, I accidentally posted the wrong truth table. It was for a LM3914 instead of the LM339 circuit. Since I can't go back and edit the post, I've included a corrected version of the schematic, for both the original LM339 and the LM3914.

Mosfet had suggested replacing the LM339 comparators with a LM3914 dot/bargraph display driver, so that only one led is on at a time. Sebi's diode ROM idea looks better with the LM3914, using 27 diodes.

The partial decoding method also works well with a 3914, although it requires one more gate than the 339 circuit did (8 XORs and 1 inverter, or 9 XORs). This is with the "off" condition translated to a "0" on the display.

- CAL

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14th August 2003, 07:22 AM	(permalink)
Sebi	Yes, ofcourse.In this case no need the pull-down resistors, but the inverter inputs need pull-up resistors.

19th August 2003, 06:16 AM	(permalink)
laroche73	truth table hard to read Sorry about the truth table display in the preceeding post, the spaces got squished out. It's the same as the one on the schematic, and it's more readable there.

19th August 2003, 07:17 AM	(permalink)
czxjuren	i think that should add one led i think that should add one led

19th August 2003, 04:46 PM	(permalink)
mechie	Apologies all round laroche73 I took the liberty of a MOD-EDIT on you excellent posting simply to correct the truth table layout. It displays correctly (monospaced font) if you surround such things with the {code} and {/code} markers (note curly brackets to avoid triggering that mode here !). __________________ I need a memory upgrade ... My head is full !