I built an asynchronous counter, as shown in figure below, using Multisim v8.0.45 from Electronics Workbench. The timing diagram of the circuit is given in the 2nd figure below. In my opinion, after 1010 (see circled part), the asynchronous counter should be reset to 1110. But in the simulation result, the output after 1010 was 0010. Would anyone pls advise why? Thanks in advance.

 

I came up with the same result as you did when I did a simple-minded analysis on paper, but I ran a sim and got the same results as your sim did! The reason it does this is that, because of propagation delays, the preset ends at about the same time the last two stages get clocked. This allows both of them to toggle immediately after preset ends. You should be able to see this by probing the preset, Q, and clock inputs to each FF.

Try removing the inverters, and instead clock each of the last 3 stages off the Q* output from the previous stage. I think you'll get the results you expected (I did).
BTW, why did you use the inverters?

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Ron

 

I add inverters because I wish to make the JK FF as positive-edge-triggered (PET) JK FF. Any JK FF that has PET input clock? Or, any suggestion to modify the circuit to rectify the problem? Thanks.

 

Read my lips.
Clocking off Q* (~Q) is the same as clocking off inverters which are driven by the Q outputs, but without the delay of the inverter (unless the inverter is internal to the FF). You can leave the inverter that drives the first FF.

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Ron

 

I still could not see how the inverter will cause the problem... I got the following timing diagram. May be you could help me to understand it. Thanks.

 

Well, it's pretty obvious that Q2 and Q3 are toggling as a result of the previous stage being changed by the NAND output. I can't tell you why that is, because it is a function of the model. I posted a detailed zoom of what I am talking about below.

As I said, my sim did the same thing, and I was able to "cure" it by removing the inverters and clocking from the ~Q output of the previous stage. This works because the clocks will now arrive while the NAND output is still present, which will override the clocks. See attached schematic.

Attached Images

	clocking.gif (7.5 KB, 408 views)
	asynctr_5c_mod.gif (10.0 KB, 408 views)

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Ron

 

Do you think there is any JK FF with positive-edge-triggered input clock in the market? Thanks.

 

Not that I know of. Are you having difficulty understanding that what I described is logically identical to what you simulated?

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Ron

 

Yes... I understood. Thanks.