I refer to reference books like Tocci, Kleitz, and Floyd, but could not find an example that shows how to design an asynchronous counter.

I wish to design an asynchronous counter that repeat the following sequence:
0 -> 2 -> 4 -> 3 -> 7 -> 6 -> 0...

Positive-triggered JK FF should be used to implement the counter.

Please advise.

Many thanks.

 

If you search my posts, you will find that I did a counter design for someone a year or 2 ago. It should help you with this one.

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Len

 

I searched for 'ljcox' and 'counter', but no result. Possible to give me the link? Thanks in advance.

 

I could not find an example even after I read many ref books in library. Pls help me in the async counter design. Thanks.

 

Here are some examples. I searched on both "counter" and "flip flop"

http://www.electro-tech-online.com/v...ight=flip+flop

http://www.electro-tech-online.com/v...ight=flip+flop

http://www.electro-tech-online.com/v...light=flp+flop

http://www.electro-tech-online.com/v...p+flop&start=0

There may be others as I did not look at all of the posts in the searches.

You should be able to find a starting point by reading these posts. If you need more help after that, just ask.

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Len

 

that is not a counter you want. a counter count 0-max number without skipping any. what u need is a counter that counts the amount of figures u want in total ie:
0 -> 2 -> 4 -> 3 -> 7 -> 6 -> 0
needs 6 states. u then feed the numbers 0-5 to a logic circuit that for each input number will give the required output number.
an ordinary counter will not do what u are asking unless the word counter has changed meaning sine i studied them 2 weeks ago

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I AM the exeption that disproves the rule in many ways but the rules still apply (unfortunately)

my site:www.simons-photography.com
http://rushdenrotaract.org.uk

 

This is not necessary. It is possible to design a counter to count in the required pattern without the need for converting logic.

For example, see http://www.electro-tech-online.com/v...light=flp+flop

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Len

 

well by the time all the various gates are added and it is worked out (not an easy task - for me anyhow) won't my suggestion be faster with the same amount of circuitry ?

__________________
I AM the exeption that disproves the rule in many ways but the rules still apply (unfortunately)

my site:www.simons-photography.com
http://rushdenrotaract.org.uk

 

Yes it may be quicker, but that is beside the point. I would have thought that you need the experience of designing a state machine.

Besides, I expect you will need more gates to do it that way. The objective of electronic design is to produce a workable design with a minimum of hardware, ie. minimum cost.

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Len

 

yes true. unfortunately i'm not that good in dealing with flip flops in this way. when i finally manage to get a bread board i'll be able to experiment a bit

__________________
I AM the exeption that disproves the rule in many ways but the rules still apply (unfortunately)

my site:www.simons-photography.com
http://rushdenrotaract.org.uk

 

Hey, Student2005 .... how about some more information here just to satisfy my curiosity (since I've been an electronics teacher for 23+ years now) .... is this just something that you want to do just for kicks (which is OK) or do you have a demented teacher who's dumping some weirdo crap on you for a project before he/she even teaches you about synchronous counters, altering modulos, stopping on-count, presetting, resetting, etc. In other words, is there an ultimate point to this weird "count" sequence? It's far more practical for a project to design a counter for a 12-hour clock from standard TTL or CMOS logic -- not as easy as one first assumes.

Dean

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Dean Huster, Electronics Curmudgeon
Contributing Editor emeritus, "Q & A", of the former "Poptronics" magazine (formerly "Popular Electronics" and "Electronics Now" magazines).

R.I.P.

 

well said

__________________
I AM the exeption that disproves the rule in many ways but the rules still apply (unfortunately)

my site:www.simons-photography.com
http://rushdenrotaract.org.uk

 

Well... It's a past question from a university. Do you have any idea? In my opinion, it's not easy. Am I right? Thanks.

 

It is not very difficult. You make a "next state" diagram as I did in one of the examples I gave you the URL of above and then produce the Karnough maps of the J & K inputs.
There is no point in us doing it for you otherwise you won't learn.

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Len

 

In your case, what's the input to the positive-edge-triggered of each flip-flop? Thanks.