Im afraid that I don't understand your question. Please elaborate.

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Len

 

For synchronous counter design, we know each FF is connected to the same clock source. For asynchronous counter design, e.g. the output of first FF is connected to the clock input of the next FF. Therefore, in your design, what's the input to the positive-edge-triggered of each FF? Thanks.

 

I have thought about the asynchronous counter and I have concluded that it would be better to do it as a synchronous counter. In order to do it as an asychronous counter, the Ck inputs to each FF would need to be gated with one or more outputs of the FFs and the clock signal.

This is because in some cases, the only signal that changes is the clock. For example, from state 7 to 6, FFa has to go from 1 to 0, but FFb and FFc do not change.

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Len