e-l-e-c-t-r-o

Oh, let me see if I got your question :?

The input signal I designed in the graph we can assume to occur due to another signal before it.
Meaning, that dc voltage variation could come from a signal before it that has a fixed time of occurence (this is why I reffered to the system as "one-shot"); let's say 15ms.
For example, it may be an analog sine wave. :shock:

The sine wave could have different peak levels that are converted into relative DC signals (not same levels' conversion-just relative; But I don't know if that is possible ops: ).

So, the real problem would be that the DC converted signal has infinite time of occurence, while the signal before it has a finite time (15ms).

In addition, a second finite sine wave can occur only after 30ms from the first (we set this as a "rule of thump", cause it simplifies the way the clamp could be released).

Considering all the above, I think the simplest (if not the only) way to go is by setting a fixed time period for the external stimulus to reset the clamp.

Assuming the input signal takes its maximum level in no more than 15ms, then the capacitor discharges around the 25th millisecond. :idea:

So, the input can be stopped to be clamped after the 26st millisecond 8)
The circuit could understand IF & WHEN an input clamp has occured, and release the clamp after a fixed period of time.

(The trick in such operation success is a "rule of thump" we can set:
That the input lasts for 15ms, and another input signal can occur only after 30 ms from the first one. 8) )

Now, the big question is of course HOW that can be done :roll:

Despite of designing the exact operation, which I am sure you can do far better than me,
I think another base in deciding not to reset the clamp while the capacitor is discharging could be the one I mentioned in my previous post:
the circuit's ability to compare the input/output levels, and be aware when the one becomes greater than the other. :shock:

In plain English, the circuit should understand that an input clamp has occured, and decide not to release that clamped until the output level becomes less than input one.

Summary: The whole concept is that a "one-shot" input occurs (i.e a sine wave), convert its peak fluctuations into (relative) DC level fluctuations, then charge a capacitor linear to produce a "one-shot" sawtooth waveform, while clamping both DC level and capacitor voltage so that a second "one-shot sine wave" can occur after a certain before of time from the first. 8)

Roff

That's too complicated. I'm still not really understanding you. I don't have time to figure out what you want and then design it.

__________________
Ron

e-l-e-c-t-r-o

:cry:

Ron H, I have given som thought and made it pretty straightforward.

Here is a graph with all the stages.

The stages are:

1. An- of "random occurence"/"random voltage level" Signal (Any kind of random sine or triangle wave, i.e a sound)

2. The signal is fed into a circuit that transforms its "corners" into DC levels.
(Unfortunately I don't know how to do that ops: Maybe it can be done with some kind of rectification :roll: )

3. The DC level signal goes into a V-I converter that charges a capacitor linearly.

NOW, the problem here is that due to the step 2 process, the first input greats a DC voltage output that lasts FOREVER (Remember that!)

The next input cannot be inserted unless there is some kind of "input disconnect" from the circuit.

The same applies for the linear charging capacitor!

The cap charges up to the V-I operational point.

The system looses a vital info about the differences of maximum voltage level between different inputs in stage 1 :roll:

4. The linear charging capacitor is discharged when the dc voltage (input to the V-I) is equal with the voltage across the cap.
In addition, the DC voltage (input) is also clamped to zero as long as the (decreasing) cap voltage is greater than the clamped DC;
OR
for a fixed time set by us, preferably 25-30ms after the time point where the voltage clamp started. 8)

Here is the graph.
Thanks for helping out :lol:

Attached Images

1111.gif (9.9 KB, 546 views)

e-l-e-c-t-r-o

At least someone here to suggest a theory frame?

Like a block diagram or something. :roll:

Great thanks for the help. :wink:

Roff

See if this will work for you. It works in simulation with a DC control voltage. I had to set an initial condition for the voltage on the ramp cap (.IC v(cap)=0). Otherwise, it didn't run as a VCO.
The input voltage isn't clamped. Instead, I cut off the current in the first VCCS (R11, D5, D6). It should work better than a clamp.
See if you can figure out how it all works.

My problem is, this has gotten so complex that it is no longer trivial. I actually have to spend time designing, and I'm pressed for time.

Attached Images

vco_sch2.gif (16.0 KB, 515 views)

__________________
Ron

e-l-e-c-t-r-o

I must admit your help has been more than enough ops:

A BIG thank you, man, you deserve it! 8)

Considering you have designed a schematic, may I put you into trouble in asking you to declare a LITTLE general theory into the schematic?

You see, I have been trying today to simulate it, I haven't been able to do so, I am afraid :roll:

The signal I am getting across the cap is linear, greater slope for greater voltage, but the cap does not discharge (in my sim)

I understood the parts that are described on the schematic (those included in dotted boxes), however I cannot manage to comprehent the other parts.

For instance, I read about flip-flops too, but I could not see how that helps for the capacitor to discharge and for the initial input to be "disconnected" from the circuit.

A block diagram with all the steps/stages and a title for its stage is all I am asking, I think :roll:
And if it is easy, could you please put into your simulation the 3 different inputs depicted in the graph below?
I think the best way for me to understand if the circuit does what I thought it could do is to see the in/out graphs.

Many thanks, again.
Sorry if I spoiled your precious time.
:roll:
Well, I think you have helped in forming me into a better circuit designer :!: (if I am at all that ops: )

Attached Images

222.gif (2.6 KB, 503 views)

Roff

I made one error in the schematic. It works as I drew it, but I'm posting a new schematic with the inverting input of U5 connected to C1 instead of ramp, which is the buffered output. It will be easier to describe the operation with this change.

I also realized that it would probably be better to connect the output of U3 to the PRESET input of A1, and tie the CLK input to GND. This should prevent the potential lockup condition which can occur, at least in the sim, and maybe in hardware. I solved it in the sim by setting .IC v(cap)=0. I didn't make this change on the new schematic.

I can't sim this now, because the file is in my computer at work, and I'm at home. I'll try to describe how it works.

You already know how the VCCS, the current mirror and the voltage follower work.

Q6 and R12, when Q6 is on (it is initially off), provide the current sink which will discharge C1 linearly. U3 is a comparator that senses when the ramp exceeds the control voltage. When this occurs, U3's output rises abruptly (guaranteed by the slight amount of positive feedback through R6), clocking a logic "1" (vcc on the D input) into A1 and causing A1Q to go high (vcc) and Q/ to go low (0V). This forces about a milliamp through D5 and D6, cutting off Q1, which in turn shuts off the current into C1 (this is equivalent to clamping the control voltage to zero, but is easier). At the same time, current ceases to flow through D3 and D4 (Q/ had been high and is now low), so Q6 turns on, discharging C1 with a current of about (9-0.7)/82k=100uA. C1 voltage slopes in a negative direction until U5 senses that it has gotten to GND (which is on the + input pin). When this happens, U5 output goes positive by 2 diode drops (approx +1.2V), clamping C1 to zero volts by diverting the discharge current, which was flowing through C1, through D1 and D2. With 1.2V on the U5 output, Q3 turns on, which turns off Q4. This applies vcc to the CLR input to A1, causing the outputs to switch states. This turns off the discharge current sink Q6 and simultaneously enables Q1 once again (by cutting off D5). If a non-zero control voltage is present, C1 will begin to charge again. If the control voltage has gone to zero (as you showed in a previous post), C1 will float, and may slowly charge due to U1 and U2 offset voltages and U4 input bias current (it can't discharge further, because U5 prevents it). Floating is not desirable, but it is one of the scenarios you proposed.

I hope this makes sense. I'm gonna be out of town for the rest of the week, starting around noon tomorrow.

Attached Images

vco_sch3.gif (16.0 KB, 489 views)

__________________
Ron

e-l-e-c-t-r-o

I'll take it home, sim it, study it a little bit, and let u know today. :lol:

Nice theory explanation. 8)

The only thing I did not quite get is the "floating" thing at the end :roll:

I am a little concerned about the "non-control voltage" state. :?:

That thing about the slow charge of the capacitor. :?
I think it should not be there :roll: Can you explain a little bit?

Last but not least, would you mind putting the different control voltages into your sim, at some point of time before you leave?

It would be vital to have in/out graphs of a "working circuit"; since I did not manage to make mine work and yours is, what about you simulating it?

Thank you.Best circuit designer I 'd ever thought I could discuss with. 8)

Roff

I changed the connection from U3 output to A1 PRE, as discussed above. I ran the sim for two different input scenarios, as shown. If you need more, you'll have to figure out how to run the sim.
With zero control voltage, the ramp actually oscillates between ~+18mV and -18mV (this occurs during the time I predicted the "float". I was wrong. ). The control loop tries to keep it at zero, but propagation delay around the control loop makes it oscillate. This could be minimized by using faster transistors (Q3 and Q4), faster op amps (U4 and U5), a faster comparator (U3), and a faster flip-flop (A1). Using a faster Q6 would be of little help, because it doesn't saturate (no storage time).
Various other schemes could be devised to speed up the loop, but I think it is impossible to totally eliminate the oscillation, due to the digital device (A1) in the loop.

Attached Images

	vco_sch4.gif (15.5 KB, 466 views)
	vco_waves4.gif (10.5 KB, 466 views)

__________________
Ron

e-l-e-c-t-r-o

I think the oscillation is too little to cause trouble. :?

I have been simulating too, in my sim something is not working, but I bet I'll find it :wink:

Now, since in yours it works, I have the theory background, the schematics, so the A+ is in my pocket.
I'll put you all into my reference list :P
Especially Ron H 8)

With bold letters!

Anyway, one last question:

The input (control voltage), do you (by default) insert it into the circuit to "go to zero after the 5th ms", OR
the circuit does that (revert input to zero)?

I am assuming the circuit does it.

So this means everything is as I thought they could be.

Maybe I 'll spend a couple of spare weekends (maybe it takes more) building that darn thing :!:

Do you by any chance can think of potential "problems" in reality that are not depicted into sim?
Like things I should expect to might not work, or to behave unstable, or even different.
Experience matters, I think, in analog circuit world.
Would be cool to share yours with us, imo :roll:

Thank you so very much.I hope one day I can design circuits like that. :wink:

Roff

OK, I'm back.
The control voltage is not forced to zero by the circuit. It is independent. The current is forced to zero when the ramp voltage reaches the control voltage, but it is released when the ramp voltage reaches zero. if the control voltage is positive (non-zero) at that time, the ramp will immediately begin to rise.
I can't think of any potential problems, but that doesn't mean there aren't any.

Cheers,
Ron[/b]

__________________
Ron

e-l-e-c-t-r-o

Hi!!

Welcome back.

Ok, I got it this time.

I also gave my assignment to my tutor, we was suprised by its direction, I think it got me an A+
So, thank you

We manage to gave it a look together, to see how it works and what could the applications could be (if any).

He told me that as an idea it is really nice, but kept questioning the control voltage's nature and role in the circuit.

He told me that if I shall use this kind of control voltage (i.e where it reaches its max value it stays there for ever) we could have the "problem" you mentioned:
The cap we continue to charge again :?

I found your "trick" with the current (probably) the best part of the circuit (the control voltage is there but it does not "pass through") 8) ,
but the control of the initial input has to be made as a "reset input" state

Otherwise I am afraid that this beatiful circuit would have minimal practical value; which results no motives to actually built it ops:

Anyway, your help has been amazing, glad to have discussed with you 8)

PS:Any comments on a potential "work around" for this issue would be great!

Roff

I asked you specifically about the control voltage in a previous post:

Cutting off the current is equivalent to resetting the input voltage. It's what you do next that's critical.
In the last schematic, I reset the flip-flop when the ramp got to zero, because you gave me either that option or the option of using a one-shot.
A third option is the external reset (some sort of pulse input, or a switch) to reset the flip-flop, as I mentioned above. See the circuit below.

We could instead cut off the current by resetting the input voltage, but it would require an analog switch (two, to do it right), and we would wind up with the same functionality.
Speaking of functionality, I asked you several times about the usefulness of this, but you seemed to think your instructor would be dazzled by the rope tricks - never mind that we couldn't catch a steer with them.

PS V5 is still your control voltage. I just used a battery for the sim.

Attached Images

vco_sch5.gif (13.5 KB, 416 views)

__________________
Ron

e-l-e-c-t-r-o

Hi

It seems I did not pay to much attention to the role of the flip-flop.

Now I see the circuit can do what I thought it could. 8)

BTW, my tutor is indeed dazzled by tricks. :shock:

BTW, what sim are you using? I am on "workbench sim8" and I can't get it to work ops: ops:

Roff

I use SwitcherCAD III from Linear Technology. It is totally free, and is not castrated like most demo versions of simulators. However, it does require more knowledge of spice than you would need to run most simulators.

__________________
Ron