The voltage controlled current source in Ron H's vco will provide the calculated current less the base current of the transistor. Using a FET will eliminate this. Of course, you will need enough voltage to turn the FET on..
Sorry, it's nit-picking day..

 

oops...disregard this..

 

Actually, in the text with the schematic, I said essentially that:
But nit-picking is still good. It must be - I do it all the time. :roll:

__________________
Ron

 

The VCO posted is very intuitive 8)

Nice example, I tried it on in Workbench.

I think now I get the whole thing with linear charging capacitors.

One final question:

Below there is the in/out diagram workbench gives.
Plus what to I am CURIOUS of whether it can be done (and how of course)

A brief description:

Give into a Voltage to current converter (the one u suggested) the input signal (blue), charge a capacitor linear BUT
when the capacitor's voltage reaches (actually tries to surpass) the voltage level of the input signal,
SOMETHING (maybe a differential amplifier with a few extra components :idea: )
forces the INPUT signal to revert to zero and the capacitor to discharge :shock:

Extremely curious to as it can be done and how, looking forward to your comments and theory explanation. :roll:

This could mean A+ mark.

Thank you so very much, you have been more than helpfull.

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Use Google and search for "dual slope integration". This is a technique used in A to D converters, digital voltmeters etc.
The unknown voltage is used to charge a capacitor, then a known current is used to discharge the capacitor, the time taken for the discharge can then be used to determine the voltage.
(a bad description, but it is late and although I feel helpfull, my brain has had enough!).

JimB

__________________
Experience is directly proportional to the value of the equipment ruined.

 

Jim brought up a good question: How do you want to determine the discharge rate? And why do you think it will impress the hell out of your instructor when you show him this marvel of electronics? :wink:

I gotta tell you, I'm beginning to wonder if you are taking a class in psychoelectronics. I think your assignment is to see how far you can drag some hapless design engineer (me) around by his ego. :roll:

__________________
Ron

 

Many thanks JimB for the suggestion of dual slope integrator.

Found this explanation about it, and currently trying to find answers on the basis of what it says here:

http://www.maxim-ic.com/appnotes.cfm/appnote_number/634

Ron, of course I study psychoelectronics :lol:
My PhD thesis is: "Go to electro-tech-online, find Ron H, and them blow his brains out by stimulating his imagination on very technical, non practical, issues :roll:

No, I am just a normal student on signal processing methods, my tutor is the one to blaim since he told me to read "Practical electronics for inventors". ops:
A good book, but after you read it makes you wanna go to places people usually don't go :roll:

Anyway, here is why I think my tutor will be impressed:

I fed into your VCO the following input (graph), deriving the output depicted.

This made me realise that the capacitor charges and then discharges due to short circuit by the 555 time (threshold exceeded etc etc).
The discharge capacitor then starts to recharge until threshold is reached again and will be discharge and then will start to charge again and SO ON.

(Right?)

This means I understood the VCO's operation.
But, I noticed that the output continues to exist even when the input reverts to zero, so i figured what if I can suggest ways to stop that?
(It will be like a "one-shot" sawtooth generator.)

If I can suggest ways to do that, and explain how these work, then NOT ONLY I comprehend the linear charging capacitors/VCOs theory, but I am able to ACT UPON those circuits.
This means expertise knowledge, imo.My tutor will be delighted, since his is into "entering bizarre electronics' field" 8)

I think my question is pretty straight forward, maybe not practical, but certainly intriguing :roll:

By the way, can you think ways of integrating into what I am asking the dual slope integrator?I think it is a good idea (but may not be needed).
Oh, not to forget to mention that the discharge rate should be fast enough to discharge the cap in time close to the charge one.Pretty simple.
We would want that in order for the whole system's process to be easily repeated.
If the discharge time is too much, then a new input signal could not be entered.

Thanks for helping out.

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When I ran the sim with zero volts on the input, the ramp output rose exponentially to 1.9V. I think the results of a sim will depend on the models you use, and actual hardware will behave somewhat differently.

So what do you actually want to do?

__________________
Ron

 

Oh,yes I noticed that difference.In my sim, the cap is charging linear.
What could likely occur in real case?

Maybe the first peak in my sim was as much as all the others.Yeap, it was, i think.

I just want to know if there is a potential for a schematic that does what the graph shows :?

In summary, various input voltages (pulse-shaped) are entered into a V-I converter, which charges a capacitor linear.
Then when the voltage across the capacitor tries to exceed the input voltage, a circuit component (DA, or 555, or dual slope integrator :?: )
"clamps" both input and output to zero; so that the system can except a signal at its initial input again. :shock:

At least let me know how much impossible that is. 8)
I was thinking of it as a "one-shot" sawtooth waveform generator.

And thank you :!:

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Do you want the cap do discharge linearly (constant current), or would exponential (resistor) be OK? If you want a constant current, we will probably have to add a negative supply.
I'm assuming that the input voltage is an independent variable. What does the input voltage do when the cap voltage gets to zero? Does it stay at zero? I believe you mentioned a one-shot ramp generator. It may be easier to simply divert the charging current to GND instead of clamping the input voltage to GND.

BTW, do you have a time limit here, or can you keep fooling with it 'til the cows come home?

__________________
Ron

 

Hi, I am back! (A lot of study for the past two days) :?

Ok, here is a graph from my sim when I feed the input into the VCO.

As you can see, no input works as what I think we can come up with. :cry:

While reading the dual slope integrator, I came up with the perception that a DSI could be used in conjuction with the V-I converter you designed.

I searched into the internet for a DSI and found these two:

http://www.rotgradpsi.de/mc/8051dev/dslopen.gif

http://www.rotgradpsi.de/mc/8051dev/dslope.gif

Could they be of any use (at least I could use that to propose to my tutor the base-theory of what I could do to make my idea come true :roll: )

Still, I don't have the theory base (the main idea) :cry:

My assignment is due in a few days .So I am kinda in a hurry ops:

Now, about your questions.

It could be nice for the capacitor to discharge linearly.I don't mind with the dual supply.Unless there could be a drawback there. :roll:

The whole concept of "forcing" the input to revert to zero is for the whole system to be able to "except" an input signal again (especially smaller ones).Considering this condition to be met, can you find the appropriate answer :?:
IMO, the input's "clamp" should occur only at one condition, when the capacitor's voltage tries to exceed the input voltage level (at any given time, during variable input voltages ).
Any time that capacitor voltage is less than the input voltage, there is not clamp to the input voltage. :shock:

I shall answer your last technical question in another post (need to depict the answer in a new graph :roll:

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See this graph.

It is the output I want to have as time evolves and as input voltages change in level as well as when "time of voltage level change" changes. 8)

Fuels into imagination deposit, 3, 2, 1, GO!!! :!:

Help appreciated. :P

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The trouble with the dual slope integrator is that, IMHO, you dont have time to do it. It requires counters and logic (or something like a PIC) to implement it. And an op amp integrator is a MUCH better way to do it. See this Maxim app note.
Regarding your last post - If you clamp the input voltage to zero, what is going to cause that clamp to be released? Are you going to do it with a mechanical (pushbutton) switch, or does it release after a fixed period of time, or... :?:

__________________
Ron

 

As the graph indicates, the clamp-release occures after "change of condition between in/out voltage levels".

You can see that the clamp condition starts when the output (capacitor voltage) gets greater than input voltage.
The clampl of both in/out occurs until the point where the output becomes less than the input.
Of course, that operation requires the input voltage to be clamped much more drastically than the output 8)

Is that possible? :roll:

 

I don't think you understand my question. Where does your input voltage come from? When the input voltage gets clamped, it doesn't go away, like the charge on the cap does when it gets discharged. The input voltage is still there - it is just "disconnected" from the input. If you release the input clamp as soon as the cap discharges, the cap will start to charge again. Then you have an oscillator, as we have discussed. If, on the other hand, you latch the input clamp, you will need some sort of external stimulus to reset the clamp.
I think the key point I'm trying to make is that the input voltage is (in my mind) an independent control voltage. If it goes to zero when you clamp it, how does it assume a non-zero value some finite length of time later?

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Ron