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Eqaully TheOne this was inherint in the previous design (if not worse) and is why I mentioned the heating of the FET's probably due to shott-throughs in a leg. My approach with appropriate tuning (with limited control signals) will remove the shoot-throughs | ||
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| sorry for the late reply ( is the forum server giving problems? cant seem to log on) Im not really good in my electronics, my looking at the new circuit u guys pain-stakingly posted, please inform me if im wrong about this. When LEFT pic input is HIGH, Q1 would be ON. While RIGHT pic input is LOW, Q4 is ON. Then, current flows from left to right. If LEFT PIC and RIGHT PIC is LOW, are both Q3 and Q4 ON? (pls correct me about this, i thought that this wasnt allowed for H-bridges) Furthermore, im limited to a single PWM channel Another thing to note is I would be using standard mosfets except for the logic level mosfet i posted earlier located at GND. Is putting a Logic level mosfet at the GND an unwise move? LAstly, in the circuit u proposed, i dont get this part. What is this for? THX alot. u guys are great help | |
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| The only condition in a H-bridge that are not allowed is a leg being on (IE a shoot-through) That is Q1 and Q4 or Q3 and Q2 as I have numbered them When the Left input is HIGH and the Right input is LOW Q1 is ON and Q2 is ON thus current left to right When the Left input is LOw and the Right input is HIGH Q3 is ON and Q4 is ON thus current right to left. As you can see the driving signal is the compement of each other. So you only have one PIC output available, just use a trasistor as an invertor to make the complement. No for the case that you mentioned when both inputs are HIGH, then Q1 and Q3 are ON (other 2 are off) All this is, is a zero-volt loop around the motor via the top switches/diodes Equally if both inputs are LOW then Q4 and Q2 are ON and you have a zero-volt loop around the motor via the bottom switches/diodes. Now there will be a problem (during powerup) IF you decide to use an iverter to generate the compment PWM. BUT if memory serves me correctly you had one PIC output to drive a disconnect/disable FET. This is not needed anymore and thus you can use that output to drive the other H-bridge leg and in the PIC code have a bit of cod ethat for diable output both as LOW. As to the final point about what is the battery and the 100mF cap. It is exactly that. You said this wat to run form a battery (or some other voltage source) that I assume you can discconect via a swithc somehwere. However, you still need a DC-link cap. For the acceleration and the sudden changes in load the battery probably wont be able to source all the charge, the cap acts as a firmer source - has to very close to the H-bridge. Probably doesnt need to be a big as 100mF but suitablly sized for the ripple current that you will be seeing | |
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Did i mention that i was using the PIC's PWM? Although my PIC has already 2 channels, my plan was to design a H-bridge that only requires 1 channel. (something like the L298 chip). That was why i connected the PIC PWM directly to the logic level MOSFET. But it failed to work. | ||
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| Lets go back to your topology: I appreciate that you have only One PIC PIN (the PWM pin) BUT in your figure you have 2 signals comming from the PIC. PWM You have a "PWM Pulse" and a "PIC Input" I take it by "PIC input" it is actually an output from the PIC? So you do have at lest 2 pins available? Right Now you are saying you are using "PIC Input" as some form of H-Bridge direction signal? and the "PWM Pulse" as your driving pulse? PIC Input LOW With "PIC Input" LOW The no matter what the "PWM Pulse" signal does no current will flow PIC Input HIGH With "PIC Input" HIGH there is a problem. With PWM Pulse LOW: There is no path for current to flow around the supply - ok BUT you have both top FET's ON!!! Zero-loop across the motor, that ok. BUT you are also supplying gate voltage to the bottom FET's They are now ON!!!! the only saving grase is there is no close-path for the supply current to flow However, When PWM Pulse is fired and thus turning on the lower FET you now are A 5 FET's on and effectivley a short across the supply I fail to see how this is ever expected to work, upless I am missing soming The only way this would work is IF each side "PIC Input" was their own signal, complement of each other which from what you are saying they dont. Please If I am mis-understanding how you are driving this please correct me, it is my week off and I am just spending the week getting drunk watch DVD's. But I have seen no H-bridge topology where it is driven like that. You always need the complement PWM Thus what I am saying is scrap the bottom FET, this now gives you TWO PIC output pins. feed one of these signals to the left input and the other to the right. The difference between the two signals is that they are the complement of each other. 50% duty => Net current = 0 >50% duty => Net current >0 <50% duty => Net current <0 Scrap your bottom FET and your circuit should work. Use mine and you have the benefit of dedicated gate-drive and tuneable shoot-though protection. | |
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My PWM tutorial uses such a scheme, you can use it with either one or two direction pins - simply ignoring the second pin is your H-bridge doesn't require it. Quote:
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| ok fair enough Nigel, not a PIC man myself (analogue and power) But as it stands Fabbies implementation will not work and will burn something out It might be simpler my way though. Feed one PWM to the LEFT and another to the right. Effectively the way Fabbie is trying (and you have describe) using the PIC inputs (complements of each other for the left adn right) you are still effectively PWMing with them, just disconnecting the power at the bottom. This does have the benefit of the free-wheel path is now a zero-volt loop meaning current wont decay as fast as if it was around the supply (in the way I have) | |
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That is also the extra logic I mentioned previously, allowing a single pin to control direction. | ||
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| Soz Nigel an edit | |
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| Not bad. All I did was scale down one of my 20kW H-Bridges so might have missed that sneaky method. BUT present topology still has the gate-drive problem. That is why I would prefer my method - ensuring FET's are hard-driven | |
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| Ahh I see what you mean by the loss in resolution (see I am not a PIC man) For an 8bit PIC 2^8 = 258 My method has direction coded into it so effetively In one direction (LEft to right say) PWM at a certain duty will give a certain voltage So 12/128 = 93.75mV per bit Now for the other method that you explained 12/256 = 46.8mV per bit. I'ts not to bad of a resolution. OK the resolution wil get worse with increase DC-link voltage BUt then you wouldn't drive it that way | |
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The PIC PWM is 10 bit, so it's actually 1024. | ||
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| OK revision: 2^10 = 1024 My way => 12/512 = 23.44mV per bit output voltage "your" way => 12/1024 =11.72mV per bit output voltage still I dont see the halving of resolution as a problem. Could you then explain one thing. Quote:
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| i dont want to interrupt the ongoing discussion here but ive found a H-bridge circuit and its driver in the August 2004 issue of EPE. what are your comments about it | |
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