digital comparator in VHDL for CPLD - Electronic Circuits Projects Diagrams Free

patroclus · 5th September 2004, 03:07 PM

It migth be stupid...
I'm trying to make a 8 bit logical comparator in VHDL, but ISE (from Xilinx) keeps on giving me messages like

WARNING:Cpld:1007 - Removing unused input(s) 'CLK'. The input(s) are unused
after optimization. Please verify functionality via simulation.

The global sketch is something like

Code:

entity Comp is
    Port ( LBus : in std_logic_vector(7 downto 0);
           Trigger : in std_logic_vector(7 downto 0);
           Mask : in std_logic_vector(7 downto 0);
           CLK : in std_logic;
           Eqin : in std_logic;
           Eqout : out std_logic);
end Comp;

architecture Comp_Arch of Comp is

begin

PROCESS (CLK)
BEGIN
	IF Eqin = '0' THEN 
	IF CLK'event AND CLK = '1' THEN
		If LBus = Trigger THEN Eqout <= '1';END IF;
	END IF;
	END IF;
END PROCESS;

end Comp_Arch;

Very simple as you can see...
But ISe keeps on giving me those messages for ALL in signals...
any help?

thanks.

bmcculla · 6th September 2004, 02:52 AM

Because VHDL runs in parallel you should always have an assignment for every case. I think the problem here is since Eqout is only ever asssigned to '1' the synthisizer is trying to be smart and it just has the output pin connected to VDD. If you use the View RTL schematic button right above the check sintax button I'll bet that is what youll see. Since CLK is never used in the synthisized output it generates a warning.

in each process or entity you need to make sure you provide a case for all the outputs.

If you do

Code:

IF CLK'event AND CLK = '1' THEN 
   if LBus = Trigger then
      Eqout <= '1'; 
   else
      Eqout <= '0';
   end if;
end if;

instead of your current If statement I'll bet that it will work. The new statement says that if the two arn't equal to set the output to '0' which never happens in your version. You should also probably make Eqin a syncronous enable; you should avoid asyncronous signals whenever possible.

patroclus · 6th September 2004, 11:40 AM

Thank you very much

I solved the problem, finally.

Now, I have 3 components (entity / arch) that compile without errors or warnings. But when I try to put them all into a single component, I get again this error and can't solve it. The warning message is "XXX pin is unused", and it says that for ALL inputs in the top entity "Logic".

I really apreciate some advice! Thanks!

the code for top component is

Code:

entity Logic is
    Port ( LBus : in std_logic_vector(7 downto 0);
           Serin : in std_logic;
           CLK : in std_logic;
           CLK_ser : in std_logic;
		 Addr: out std_logic_vector(15 downto 0));
end Logic;


architecture Logic_Arch of Logic is

COMPONENT Shift_Reg 
    Port ( CLK : in std_logic;
           SERIN : in std_logic;
           QTRIGGER : out std_logic_vector(7 downto 0);
           QMASK : out std_logic_vector(7 downto 0);
           QMODE : out std_logic);
END COMPONENT;
COMPONENT Comp 
    Port ( LBus : in std_logic_vector(7 downto 0);
           Trigger : in std_logic_vector(7 downto 0);
           Mask : in std_logic_vector(7 downto 0);
           CLK : in std_logic;
           Eqin : in std_logic;
           Eqout : out std_logic);
END COMPONENT;

COMPONENT Contador
	generic(n: natural :=16);
     Port ( CLK : in std_logic;
           CLEAR : in std_logic;
           CE : in std_logic;
		 CE2: in std_logic;
           Q : out std_logic_vector(15 downto 0);
		 ENDCOUNT : out std_logic);
END COMPONENT;


FOR ALL:Contador USE ENTITY Contador(Contador_arq);
FOR ALL:comp USE ENTITY Comp(Comp_arch);
FOR ALL:shift_reg USE ENTITY shift_reg(shift_reg_arch);

SIGNAL CLEAR, CE, CE2, ENDCOUNT: std_logic;
SIGNAL Triggout, Maskout, LogicBus: std_logic_vector(7 downto 0);
SIGNAL Eqin, Eqout: std_logic;
SIGNAL Q: std_logic;

begin		

	Compa: Comp PORT MAP(LBus, Triggout, Maskout, CLK, Eqin, Eqout);
	Count: Contador PORT MAP(CLK, CLEAR, CE, CE2, Addr, ENDCOUNT);
	Shift: Shift_reg PORT MAP(CLK_ser, SerIn, Triggout, Maskout, Q);

end Logic_Arch;

patroclus · 7th September 2004, 09:56 AM

I still can't work this out...
any help please?? Thanks

How can I specify that those lines are the main circuit inputs, so I can't tell which value will they be??

bmcculla · 7th September 2004, 07:07 PM

Try something a bit simpler first.

Code:

Begin

Compa : entity work.Comp
    port map( --fill this in --);
...
end Logic_arch;

This way you don't have to deal with components. This single statement does all the instantiation for the component. Other than trying this I'm not seeing anything obviously wrong with your code. I haven't used the component structure very much though.

patroclus · 7th September 2004, 10:18 PM

Without component structure, how can I do these things??
I have a 17 bit shift register, a 17 bit counter and a 8 bit mask comparator. I implment each of them by entity/architecture, and then ??

Any other way to do ??

thanks for you help!

I'm really lost (but I worked with VHDL before in university, though never in real circuits, I can't see any thing wrong neither!)

bmcculla · 7th September 2004, 11:50 PM

If you follow the structure in my post above you can create an instance of the entity directly. The component structure makes it easy to change the implementation of the component but for general use isn't really nessesary.

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5th September 2004, 03:07 PM	(permalink)
patroclus	digital comparator in VHDL for CPLD It migth be stupid... I'm trying to make a 8 bit logical comparator in VHDL, but ISE (from Xilinx) keeps on giving me messages like WARNING:Cpld:1007 - Removing unused input(s) 'CLK'. The input(s) are unused after optimization. Please verify functionality via simulation. The global sketch is something like Code: entity Comp is Port ( LBus : in std_logic_vector(7 downto 0); Trigger : in std_logic_vector(7 downto 0); Mask : in std_logic_vector(7 downto 0); CLK : in std_logic; Eqin : in std_logic; Eqout : out std_logic); end Comp; architecture Comp_Arch of Comp is begin PROCESS (CLK) BEGIN IF Eqin = '0' THEN IF CLK'event AND CLK = '1' THEN If LBus = Trigger THEN Eqout <= '1';END IF; END IF; END IF; END PROCESS; end Comp_Arch; Very simple as you can see... But ISe keeps on giving me those messages for ALL in signals... any help? thanks.

6th September 2004, 02:52 AM	(permalink)
bmcculla	Because VHDL runs in parallel you should always have an assignment for every case. I think the problem here is since Eqout is only ever asssigned to '1' the synthisizer is trying to be smart and it just has the output pin connected to VDD. If you use the View RTL schematic button right above the check sintax button I'll bet that is what youll see. Since CLK is never used in the synthisized output it generates a warning. in each process or entity you need to make sure you provide a case for all the outputs. If you do Code: IF CLK'event AND CLK = '1' THEN if LBus = Trigger then Eqout <= '1'; else Eqout <= '0'; end if; end if; instead of your current If statement I'll bet that it will work. The new statement says that if the two arn't equal to set the output to '0' which never happens in your version. You should also probably make Eqin a syncronous enable; you should avoid asyncronous signals whenever possible.

7th September 2004, 09:56 AM	(permalink)
patroclus	I still can't work this out... any help please?? Thanks How can I specify that those lines are the main circuit inputs, so I can't tell which value will they be??

7th September 2004, 07:07 PM	(permalink)
bmcculla	Try something a bit simpler first. Code: Begin Compa : entity work.Comp port map( --fill this in --); ... end Logic_arch; This way you don't have to deal with components. This single statement does all the instantiation for the component. Other than trying this I'm not seeing anything obviously wrong with your code. I haven't used the component structure very much though.

7th September 2004, 10:18 PM	(permalink)
patroclus	Without component structure, how can I do these things?? I have a 17 bit shift register, a 17 bit counter and a 8 bit mask comparator. I implment each of them by entity/architecture, and then ?? Any other way to do ?? thanks for you help! I'm really lost (but I worked with VHDL before in university, though never in real circuits, I can't see any thing wrong neither!)

7th September 2004, 11:50 PM	(permalink)
bmcculla	If you follow the structure in my post above you can create an instance of the entity directly. The component structure makes it easy to change the implementation of the component but for general use isn't really nessesary.