csaba911 posted this schematic some time ago.

It addresses the RAM chip and WE using counters. The problem is, when counter is at zero (cleared), WE is enabled. then it gets disabled, and then it changes to address 1 and enables WE again at the same time.

Doesn't the address need to be stable before actually pulling WE down??
Does this circuit really work anyway??

thanks.

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That may depend on which edge of the /WE that data is clocked in on.

j.

 

It usually is on lowing edge isn't it?? In this case, am I wrong?

 

Looks like it's on the rising edge to me. At least on the SRAM chip I looked at (a Cypress).

j.

 

Looks like it's on the rising edge to me. At least on the SRAM chip I looked at (a Cypress).

j.

 

SRAM has a setup time and a recovery time. The setup time is how long after WE and the address are asserted you have to wait for the data to be writen. Recovery time is how long you have to wait after a write to begin another transfer. Same idea for reads. It shouldn't matter if you assert WR at the same time as the address as long as you wait the required time. I've seen some SRAMs that let you reduce the setup time if you assert the address beforehand but it shouldn't matter if you wait the right amount of time. The Data is writen or read on the rising edge of the strobe.