# Electronic Circuits and Projects Forum

1. ## Slowing FPGA Transition Times

Is there anything FPGA configuration setting or manipulation of the clock edges for FPGAs that allow you to slow down the transition times to relax termination requirements when you aren't trying to run the FPGA at very fast clock speeds? I'm curious about all FPGAs in general, but I plan to use the Spartan 3A-DSP.

Does anyone also have any idea what happens on a daisy-chained bus when each device has a series termination resistor? This paper:
http://www.electro-tech-online.com/c...Line_notes.pdf
only talks about series termination at the source. It also says "In order to satisfy Kirchhoff’s laws, a voltage wave of the opposite polarity propagates back down the line, canceling the original wave." and I'm having trouble figuring out exactly why that is for transients.

EDIT: I hunted around on some EDA boards and they mentioned something about selecting IO standards with slower transition times? And that it's bad practice to do things like add capacitors-to-ground to the line, or add RC filters to slow the transition time (which is rather impractical anyways since you have hundreds of IO running around). Especially for the capacitors-to-ground it since it seems like it could easily start to increae heat on the drivers. Anyone care to elaborate or add their own thoughts?

2. If you are trying to run the FPGA at fast clock speeds, then you likely need the fast transition times to maintain signal integrity. It's poor practice to try to degrade the signal just to allow for poor transmission line design.

If your read further, the statement "In order to satisfy Kirchhoff’s laws, a voltage wave of the opposite polarity propagates back down the line, canceling the original wave." refers to having a short circuit at the far end of the line. The next paragraph talks about the far end being open circuit (b), which is the case for a typical digital bus application.

On a daisy chained bus, only one output source is active at a time, the other outputs are in a high impedance state. Thus the line only sees the series termination of the active output. (A series termination is only used at the output, not the input).

For added explanation look at the paragraph on Pg. 5-6 titled Series Termination (of Transmission Lines) in this.

3. I was wanting to run the FPGA at slower clock speeds for more relaxed timing requirements during routing and the system itself isn't all that fast anyways. But if the transition times of the FPGA are fixed for realy high clock speeds, then I have to deal with terminations that ultimately aren't needed. These things can run at like 250MHz but I only really expect to need MCU speeds really...50MHz tops, usually 25MHz.

4. A reasonable rule-of-thumb for transmission line effects being a problem on a circuit board is when the transmission line length in inches is greater than 3 times the signal rise-time in ns.

You could slow the signal rise and fall times by adding a series source resistor of about 100 ohms with a small capacitor to ground. For example 50pF would give a rise/fall time of about 5ns.

5. Hi dknguyen, There are ways to slow down the transistion times of the I/O's if that's what you want to do. You can set slew rates on most FPGA I/O pins. You would set the slew rate in the .UCF file for your project. If you need more help, I'll try to look up how to do that.

6. THanks, that all I Needed to know...for now...

...

7. When I worked at Qualcomm Inc. It was standard practice by all engineers to use a series resistor on the source and a RC shunt on the termination. If a a daisy chain was in the picture the source series resistor was still used and the RC shunt was placed at the end of the chain See attachments.
Note: we only did this on critical nets that drove edge triggered devices such as clocks, read/write etc. data lines and address bits not such a concern as it is assumed they are stable already. This technique is really not used to slow slew rates, but rather ringing overshoot and undershoot associated with high speed signals.
During signal quality test using DSO and low inductance ground lead probe of critical nets, if the Series R was found to not be needed we would use a 0 ohm resistor, if the shunt was not needed we would make it DNI (Do not install).

And yes I do recall when using Xilinx Virtex parts, we could set the slew rate of the I/O. I am sure each FPGA manufacturer has their own way of setting that feature.

Also see Howard Johnson;s comments (Renowned High speed logic designer)
http://www.sigcon.com/Pubs/news/2_24.htm

8. Yes, I am just trying to decide whether to have series resistor termination placeholders or not. Especially since I don't know and can't measure the characteristic impedance of the trace beforehand. I might just end up slowing the slew rate and limiting the clock speed.

I was considering making stackable modules but that brings up termination problems since now you have daisy chains and series resistors won't work anymore. It'd be easy enough to build a simple module to plug into the top of the stack that provides parallel termination for such a case though, but that still leaves an unterminated stub betwee the B2B connector and FPGA pin.

Vague question, but If I turned slew rate to maximum and just stayed around MCU speeds, what is the likliehood that I'd have to inspect all the signal lines with an oscilloscope to make sure there was no ringing and that termination might be needed? It's not really standard procedure to do on "most" microcontroller projects. I'm just trying to gauge just how big of a problem it might be.

Mikebits-
is that series R still present with the parallel termination in the daisy chain just to relax the matching requirements of the parallel termination? I read that parallel terminations are more sensitive to placement than series terminations because in any case series termination will dampen ringing on the entire line.

9. Mikebits-
is that series R still present with the parallel termination in the daisy chain just to relax the matching requirements of the parallel termination? I read that parallel terminations are more sensitive to placement than series terminations because in any case series termination will dampen ringing on the entire line.
I will start with the placement question. Placement is not real critical but it is always best to place the shunt termination as close to the termination point as possible. For your first question; in general practice I have always laid the pads for series and RC shunt terminations and ended up either using a 0 ohm for series with RC or some series R and DNI for the shunt. Only in case with really long ugly lines have I needed both. Adding 0805 pads is cheap, easy, and uses little space. Simpler to plan ahead, and stuff a zero ohm or make a DNI than re-fab the board.

10. I was considering making stackable modules but that brings up termination problems since now you have daisy chains and series resistors won't work anymore. It'd be easy enough to build a simple module to plug into the top of the stack that provides parallel termination for such a case though, but that still leaves an unterminated stub betwee the B2B connector and FPGA pin.
Are you saying that you plan to run High speed signals from board A to board B via connectors? This opens a whole new can of worms.

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