If you are trying to run the FPGA at fast clock speeds, then you likely need the fast transition times to maintain signal integrity. It's poor practice to try to degrade the signal just to allow for poor transmission line design.
If your read further, the statement "In order to satisfy Kirchhoff’s laws, a voltage wave of the opposite polarity propagates back down the line, canceling the original wave." refers to having a short circuit at the far end of the line. The next paragraph talks about the far end being open circuit (b), which is the case for a typical digital bus application.
On a daisy chained bus, only one output source is active at a time, the other outputs are in a high impedance state. Thus the line only sees the series termination of the active output. (A series termination is only used at the output, not the input).
For added explanation look at the paragraph on Pg. 5-6 titled Series Termination (of Transmission Lines) in this.