TTL and CMOS - Electronic Circuits Projects Diagrams Free

LAU B · 12th June 2009, 02:55 PM

hi, i am a student at WKC in my final year and am currently just finishing off my final project. i have built a fairly basic reaction timer that counts up in tenths of a second. i have used a mixture of CMOS and TTL chips in my circuit. not a good idea ,i know, but my circuit seems to work fairly well. will there be any long term deffects because of this?

BrownOut · 12th June 2009, 03:31 PM

The noise margin will be affected at the interface between ttl and cmos, if not properly accounted for. So, the unit may fail intermittently, but there shouldn't be any long term effects or degrading.

crutschow · 12th June 2009, 08:02 PM

The TTL high output level is not a full logic "1" for the CMOS. Thus the CMOS may draw more current then normal as the input PMOS transistor may not be fully off as it should be with a logic "1". (See Logic Voltage Thresholds for TTL, CMOS, LVCMOS, and GTLP IC's for a comparison of the logic threshold levels.) To avoid this you should have a pull-resistor (10kΩ or so) to +5V on all TTL outputs connected to a CMOS input.

pcbheaven.com · 14th June 2009, 07:50 AM

You should do proper interface between them to have no problem

Leftyretro · 14th June 2009, 08:42 AM

The main thing when using CMOS is to be sure to tie unused input pins high or lower, never floating free. This applies even to unused gates in multi-gate packages. With TTL you could get away with unwired inputs floating high, even though it's not a recommended practice, however with CMOS it would cause gate oscillation and over dissipation of the package.

Lefty

Thread Tools
Show Printable Version Email this Page
Display Modes
Linear Mode Switch to Hybrid Mode Switch to Threaded Mode

Similar
Title	Starter	Forum	Replies	Latest
cmos	naik_mc	General Electronics Chat	3	23rd January 2008 08:36 PM
Cmos To ttl	Eng.Remon	Micro Controllers	9	17th April 2007 09:41 PM
24v/CMOS/24v how???I	svtiss	General Electronics Chat	5	6th November 2004 06:55 AM
TTL o/p or CMOS o/p for different Vcc	Eric Koh	Micro Controllers	3	2nd June 2004 02:53 PM
TTL/CMOS	hani_a	General Electronics Chat	6	18th April 2004 06:48 PM

12th June 2009, 02:55 PM	#1
LAU B	TTL and CMOS hi, i am a student at WKC in my final year and am currently just finishing off my final project. i have built a fairly basic reaction timer that counts up in tenths of a second. i have used a mixture of CMOS and TTL chips in my circuit. not a good idea ,i know, but my circuit seems to work fairly well. will there be any long term deffects because of this?

12th June 2009, 03:31 PM	#2
BrownOut	The noise margin will be affected at the interface between ttl and cmos, if not properly accounted for. So, the unit may fail intermittently, but there shouldn't be any long term effects or degrading.

12th June 2009, 08:02 PM	#3
crutschow	The TTL high output level is not a full logic "1" for the CMOS. Thus the CMOS may draw more current then normal as the input PMOS transistor may not be fully off as it should be with a logic "1". (See Logic Voltage Thresholds for TTL, CMOS, LVCMOS, and GTLP IC's for a comparison of the logic threshold levels.) To avoid this you should have a pull-resistor (10kΩ or so) to +5V on all TTL outputs connected to a CMOS input. __________________ Carl Curmudgeon Elektroniker

14th June 2009, 07:50 AM	#4
pcbheaven.com	You should do proper interface between them to have no problem __________________ And on the eighth day God said, "Okay, Murphy, you're in charge!" www.pcbheaven.com

14th June 2009, 08:42 AM	#5
Leftyretro	The main thing when using CMOS is to be sure to tie unused input pins high or lower, never floating free. This applies even to unused gates in multi-gate packages. With TTL you could get away with unwired inputs floating high, even though it's not a recommended practice, however with CMOS it would cause gate oscillation and over dissipation of the package. Lefty __________________ Measurement changes behavior