I have been working on a full-bridge inverter in Pspice for quite some time now. My goal is to use PWM at 18 kHz. I have used two 741 op-amps as comparitors to compare a 60 Hz sine wave with a 18 kHz sawtooth wave. The result, when filtered correctly, should give a 60 Hz output.

Here is a link to the circuit setup and the waveform I am getting:

http://www.ece.msstate.edu/~mw7/full...e_inverter.JPG

http://www.ece.msstate.edu/~mw7/full...e_waveform.JPG

The problem is that the output will only increase to 20 volts (peak-to-peak). I realize the schematic only has 10 volts as the source. However, the problem occurs with any voltage greater than 10 volts. I'm almost positive that the two upper bransistors have to be connected from gate to source. Does anyone know how this can be done using the op-amps? Is there any other possible way?

I also have PSPICE schematic located at the following link:

http://www.ece.msstate.edu/~mw7/testh.sch

I greatly appreciate any help.

 

You have two things contributing to this situation:

1. When the 741 output is high, it will only get within 1 or 2 volts of Vcc. In your circuit, this means it will get to around 11-12v.

2. M62 and M64 are source followers. The source will only go as high as the gate, minus a couple of volts ( the exact value is dependent on the characteristics of these MOSFETs. Remember that, in order to turn on a MOSFET, Vgs must be greater than the threshold voltage.

The easiest solution is to change M62 and M64 to p-channel MOSFETs, and change the phases of their gate drives (f to M62 gate, c to M64 gate). The voltage on the gate needs to go to the positive rail (10v in your schematic) to turn them off. If you increase the 10v supply, you have to increase Vcc.

The 741 is not suitable for driving monster MOSFETs. That transistor has a gate capacitance of 3700pF, and each 741 is driving 2 of them. The 741 output is limited to about 25ma. Dv/dt=I/C, which means your gate slew rate (SR) is going to be

SR=2.5e-2/(2*3.7e-9),
SR=3.4v/usec (Due to Miller effect, it will be slower, but this illustrates the point).
This means it will take several microseconds for your transistors to completely switch. At 10% duty cycle, your pulse width is only 5.6usec. The transistor dissipates a lot of power during switching, so you need to minimize gate rise and fall times.
You should also probably consider having some dead time (100ns?) between c and f. otherwise, you potentially have short periods of time where you have both transistors on one side of the bridge conducting.

You need two rail-to-rail drivers for your bridge, and they each need to be able to source and sink several amps transient current.

 

as stated above change to a P-N type legs that will sort alot of yr probs - this will only work upto a DC link bus of upto the Opamp

For higher vlotages think abt making a kind of floating gate drv - then you can use all N-types

Try putting a NPN-PNP push-pull output stage to act as a gate drive to the MOSFETS. Also why not use a proper comparator the LM111 is pretty good comparator that comes with SPICE.