Hi,

I'm using the following parallel port programmer cable:
http://toolbox.xilinx.com/docsan/2_1.../jtg/fig26.htm

I've implemented this circuit and have setup a 44pin plcc socket to test on. I'm using "iMPACT" software which is part of the latest WebPack ISE package given away for free on the Xilinx site. The software seems to recognise something is connected:

Connecting to cable (Parallel Port - LPT2).
Checking cable driver.
Driver windrvr.sys version = 5.0.5.1.
LPT base address = 0378h.
Cable connection established.


Then, when I proceed to attempt a chain init, it prints:

Identifying chain contents ....
'1': : Manufacturer's ID =Unknown
INFO:iMPACT:501 - '1': Added Device UNKNOWN successfully.
----------------------------------------------------------------------

...and continues infinitely, incrementing the device # each time.


I'm not sure what's wrong with the circuit or software or what I'm doing...if anyone has had previous experience with this - please help

 

What is the length of your Parallel Port Cable?

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Less than 2m - I think that's the limit....

 

are you using a xillinx cpld? Device ID is located on the chip. Either that, or you've got incompatible cable.

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Yes, I'm using a 44pin Xllinx 9572 CPLD - common chip...and I realise that it should automaticall be recognoised and added as an icon to the screen but it doesn't...I don't know why...I've dbl checked the circuit wiring, it looks ok, I've shortened all the lead such that the entire set of connections from parallel port to cpld is less than 40cms...not sure what else to do...what other things should I check for???

Thx,
Avital

 

Is 0x378 the address your LPT2 port? Because most of the parallel ports that I've worked on have 0x378 for LPT1. Check this out.

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Yes, I've considered this...I changed it back to lpt1, made sure that my bios is set to "bi-directional" and that pnp emulation is setup. Basically, I did everything I could find on the Xilinx site. This is very odd, because I've seen this schematic (modified slightly even, in some) in 3 diff. places. It's still on the Xilinx website and is explained fairly well...not sure what else to do. Have you actually made this simple circuit and managed to get it to work???

 

No I haven't made it but I am aware of problems with parallel ports. I have 3 parallel port based device programmers lying in my junk. They all had some or the other problem. . Changing the Parallel port modes use to affect their working even though non of them used bi-directional feature.

Check this schematic with that of yours.
http://www.xilinx.com/support/progra...es/0380507.pdf

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Yup, that's the one I'm using as my main source - I just checked others to make sure. I think it may be noise problems on the JTAG lines...even though there are caps on those lines - considering a schmitt trigger. Any other ideas on the problem may be? Any pointers on parallel port interfacing musts?

 

Try changing your LPT1 mode to "Normal", ECP, EPP or ECP+EPP in BIOS and check your software for each different mode. If you still can't get it, then I think your CPLD is faulty and not responding to ID request. Replace it.

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I've already tried all of those, and I've consulted the Xilinx website about that too - I really don't think it's the lpt port itself. From what little I could gather on newsgroups, there may be a problem with the circuit in general as the HC125's are extremely sensitive to noise. I'm considering 7414s and/or caps on the inputs to the 125s. But, before I start soldering stuff again I was wondering if anyone could suggest some ideas on this issue of noise.

Thx,
Avital

 

Well, in order to minimize noise in your system following care should be taken
1) Your power supply should be as pure and stable as possible. Use in-line choke filters (ferrite bead) for reducing noise ripples in Vcc line.
2) Always use decoupling capacitors across the power pins of all ICs in your system. 0.1uF is suitable value. This reduces noise considerably.
3) Do not take TTL signals to very long distance. Keep distance between your PC and circuit to a minimum.

I doubt whether you have connected decoupling capacitors in your circuit because they are not shown in the schematic. If not try that first. May be it will solve the noise problem.

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"There is no way to peace, peace is the way!"

 

Actually,

I fixed the initial problem. The software now does basic functions like recognise the chip, calcs the checksum, even erases the chip. However, I am not able to program anything - how long would such a process take anyway? I fixed the problem by adding a 1k pullup resistor to TDO. Was wondering if anyone had opnions on what was going on and/or has experience with JTAG and can explain this to me.

Thx
Avital

 

Hi, Snowman. The first thing I'd suggest is to check your signal levels with a scope, if you haven't done so already. Noise could be the problem, but rule out the simple things first. There's no substitute for hooking up a scope and viewing the actual signals.

As shown in the schematic, the cable buffer chip draws power from your prototype system. What are you using for the cable VCC, 3.3V or 5V? (The XL inputs are 5V tolerant). The cable schematic shows a schottky diode in series with your VCC supply -- did you use a schottky type or a standard silicon diode like the 1N914? (schottkys have a lower forward voltage drop)

A few more questions,

1) Are you driving the cable from a desktop or laptop parallel port? Again, check the levels.

2) The schematic shows a 5.1K resistor to VCC on TDO. Having to add another 1K pullup to get things "partially" working is a suspicious sign. The signal levels may be just making it, and that would explain being able to do short operations like getting the device ID, but failing longer operations like programming the device. Noisy lines can also cause this problem. Perhaps one bit out of 100K fails. When short operations work and long ones don't, it should raise a red flag (and make you pull out the scope :wink: ).

Also, a more detailed description of your prototype board setup might help (power supplies, decoupling caps & location, etc.)

I have a Xilinx PP cable that essentially matches the posted schematic (I popped the cover years ago and looked it over). It's about 3 ft long and works fine with the Virtex board I have from Avnet (two JTAG devices, 18V01 and a XC2V40).

- Claude

one more thing. I found a Xilinx databook that covers the XC9500XL chips, and it mentions that the inputs have a small amount of hysteresis, around 50mV.

 

Claude,

Unfortunately, I can't access to a scope very easily - I had one for about a week or so but it's gone now. I'm using 5V as VCC, 1N4148
Schottky diodes, and a standard PC desktop parallel port. The circuit is already soldered onto a veroboard as I thought it would work "out of the box", I'm feeding the circuit 5V from a 7805 (100mA version) along with 10nF and 47uF caps as noise filters. The input to this power supply is also a regulated 5V signal from another 7805 with some caps as my main power supply is 13V, and that exceeds that max input for the 78L05. All the leads/wires have been kept extremely short - the wires from the parallel port to the circuit is ~20cms, and the wires from the programmer to the socket board is about 5cms.

I totally agree that I need a scope but it doesn't seem likely I'll be getting access to one anytime soon. Noise and waveform problems seem to be the underlying cause from what I've gathered from the Xilinx answer site. In fact, the 100pF caps are one attempt by Xilinx the corner freq - filtering it to 100MHz. But the slope gets extremely slow, and with added noise, is much higher than 50mV so using 50mV schmitt triggers such as 7414s would not work. So, instead, I tried soldering a 1K resistor between the output/input of one of the 74125 gates, in fact, for CLK, DIN, and PROG. I've also tried a weak (1k) pullup on PROG and CTRL. None of this has worked. Perhaps using LS components with a lower switching voltage may work (I have yet to test this). I suppose there are no "canned" solutions for this type of thing.... It's strange that pretty much all works except programming.

What do you think?
Thanks,
Avital