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Old 8th September 2008, 12:20 AM   (permalink)
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Thanks everybody for your help. Being less experienced, i need to spend some more time trying to understand your tips and then i will get back to you.
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Old 8th September 2008, 02:06 AM   (permalink)
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Quote:
Originally Posted by Hero999 View Post
Before you try, I strongly recommend looking at the internal schematic of the 7555 with a load connected from pin 3 to a lower voltage than VSS.

I don't want you to waste a 555 unless of course you're got 1000s of them at your disposal.
I've some tens of ordinary 555s at disposal. (can easily get more if necessary)To get 7555s I'll have to travel to Bangkok.

Since their internal structure is almost the same (except for CMOS) they should behave similar under the given conditions.

I just chose the 7556 because of the long time delay of 180 seconds, a bit hard to achieve using a 556 because of the minimum threshold current.

The circuit is easiest to build up using one astable and one monostable. The problem is just the high voltage - used for supply it would kill the the chip within no time.

Hans
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Last edited by Boncuk; 8th September 2008 at 02:07 AM.
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Old 9th September 2008, 05:02 PM   (permalink)
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The CMOS and TTL ICs do behave differently.

If it's a CMOS IC it'll probably go into destructive latchup, if it's TTL, the base-emmiter junction of the output transistor will breakdown and be destroyed.
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Old 10th September 2008, 12:48 AM   (permalink)
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The CMOS and TTL ICs do behave differently.

If it's a CMOS IC it'll probably go into destructive latchup, if it's TTL, the base-emmiter junction of the output transistor will breakdown and be destroyed.
Do you see a big difference between dead and dead?
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