Binary counter - Electronic Circuits Projects Diagrams Free

LApprenti Sorcier · 30th October 2003, 09:09 PM

Can anyone please explain me what exactly a 14 stage binary ripple counter is?

What's with all the q's what do those outputs do?

Thanks!

LApprenti Sorcier · 3rd November 2003, 06:40 PM

Hadn't noticed the mistake... just corrected it...

laroche73 · 3rd November 2003, 08:36 PM

A binary ripple counter consists of a chain of flip-flops, with each flip-flop output (the q's) serving as the clock for the next F/F in the chain. The name comes from the effect of the input clock as it "ripples" down through the chain (think of a row of dominoes falling down, it's a pretty good analogy). The first F/F in the chain is the least significant bit (LSB) of the binary counter, the last is the MSB.

This type of counter is mostly seen in standard logic parts, like the CD4020/4040/4060 or 74xx393. Ripple counters were popular in the early days of digital logic, since they didn't require much in the way of combinatorial logic. You'll also come across the term "synchronous binary counter". In synchronous counters, all of the outputs (q's) change state on the same clock edge. Synchronous counters have largely replaced ripple counters in FPGAs and other programmable logic architectures, due to their lower propagation delays and higher noise immunity. They do require considerably more combinatorial logic to make. It's never been a problem for the "sum-of-product" architecture you find in PLDs, and nowadays most FPGAs include "fast-carry-logic" as an aid to building synchronous counters.

Take a look at the internals of a 74HC393 (dual 4-bit binary ripple counter) versus a 74HC4520 (dual 4-bit binary synchronous counter) to get an idea of the difference between the two types of counters.

btw, a 14-bit binary counter will divide an input signal by 2^14 (16384). That's why you get a 1/2 second output from a CD4060 and a 32.768Khz crystal.

LApprenti Sorcier · 4th November 2003, 02:29 PM

I'm a little confused...
1/2 second output is the same as 2Hz right?

Is this what you mean?:

Quote:

Originally Posted by Phasor

Here is the circuit to get a 2Hz clock signal, using the 4060. You will need to add a divide-by-2 on the end to get 1Hz (eg, flip-flop).

crust · 4th November 2003, 10:38 PM

Quote:

Originally Posted by LApprenti Sorcier

I'm a little confused...
1/2 second output is the same as 2Hz right?

Yes, the frequency is the inverse of the period and vice versa.

LApprenti Sorcier · 7th November 2003, 02:09 PM

Of course! LOL i already knew that, just didn't think about "period" just got confused...

Thanks a lot!!!

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30th October 2003, 09:09 PM	(permalink)
LApprenti Sorcier	Binary counter Can anyone please explain me what exactly a 14 stage binary ripple counter is? What's with all the q's what do those outputs do? Thanks! __________________ "I have not failed. I've just found 10,000 ways that won't work." Thomas A. Edison

3rd November 2003, 06:40 PM	(permalink)
LApprenti Sorcier	Fé de erratas Hadn't noticed the mistake... just corrected it... __________________ "I have not failed. I've just found 10,000 ways that won't work." Thomas A. Edison

3rd November 2003, 08:36 PM	(permalink)
laroche73	ripple counters A binary ripple counter consists of a chain of flip-flops, with each flip-flop output (the q's) serving as the clock for the next F/F in the chain. The name comes from the effect of the input clock as it "ripples" down through the chain (think of a row of dominoes falling down, it's a pretty good analogy). The first F/F in the chain is the least significant bit (LSB) of the binary counter, the last is the MSB. This type of counter is mostly seen in standard logic parts, like the CD4020/4040/4060 or 74xx393. Ripple counters were popular in the early days of digital logic, since they didn't require much in the way of combinatorial logic. You'll also come across the term "synchronous binary counter". In synchronous counters, all of the outputs (q's) change state on the same clock edge. Synchronous counters have largely replaced ripple counters in FPGAs and other programmable logic architectures, due to their lower propagation delays and higher noise immunity. They do require considerably more combinatorial logic to make. It's never been a problem for the "sum-of-product" architecture you find in PLDs, and nowadays most FPGAs include "fast-carry-logic" as an aid to building synchronous counters. Take a look at the internals of a 74HC393 (dual 4-bit binary ripple counter) versus a 74HC4520 (dual 4-bit binary synchronous counter) to get an idea of the difference between the two types of counters. btw, a 14-bit binary counter will divide an input signal by 2^14 (16384). That's why you get a 1/2 second output from a CD4060 and a 32.768Khz crystal.

7th November 2003, 02:09 PM	(permalink)
LApprenti Sorcier	Of course! LOL i already knew that, just didn't think about "period" just got confused... Thanks a lot!!! __________________ "I have not failed. I've just found 10,000 ways that won't work." Thomas A. Edison