3v0

The LAs I worked with had two modes. Sort of like sync and async.

The first is logic mode (may be another name) where you only need to know the state for each clock period. This mode is most often used in well behaved systems like a computer bus.

The second is timing mode. This works much like a scope except data is recorded as a logic state instead of an analog value. The requires a much higher sample rate.

I think Erick is talking about timing mode. This makes sense since there is little use for a 4 bit LA in logic mode.

Edit: looks like I have the names switched.

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petrv

I had an idea to build a small and inexpensive but much more powerful (100 MHz sample rate) L.A. using a small FPGA - Spartan 3E-100, costs less than $10 at DigiKey.com, USB connectivity would be provided with PIC18F2455 USB PIC micro. The HW was really simple - the main circuit contained (not counting the power supply) just 2 ICs - the FPGA and the PIC micro (which would initialize the FPGA with a configuration file downloaded from the PC). The design could be upgraded with a fast external SRAM (one additional IC).

In the end I did not do this because I was lazy to do the PCB layout - I hate doing layout for big fine-pitch QFP packages (the FPGA is VQFP-100 with 0.5 mm pitch).

Later I needed a L.A. urgently so I had to buy one - I have bought the one from INTRONIX (http://www.pctestinstruments.com/) - for almost $400 it was a big investment (for a hobbyist) but it is really an excellent tool.

So the FPGA and other components are waiting in my drawer until I find another use for them

ikalogic

Ok, that means that a 1 MHz sampling rate give me a 1 uS resolution, any change faster than than that could be *not* in the time it really changed, but at the nearest sampling point.

right?

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Ibrahim Kamal
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eblc1388

That's about right.

Nevertheless, a 1MHz sampling rate is often good enough for 95% of applications one would encounter, especially events like I/O port levels that are clocked and will change only synchronously to a common system clock.

Your main challenge in a project of this kind is writing the PC host software which would read the collected data and display them, zooming in/out, triggering and user selectable timing cursors for measurement.

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L.Chung

ikalogic

Okay then! That's exactly what i was thinking also. thanks for backing me up!

now about the PC software, i'm an 'old' visual basic programmer (before even i touch uCs) so it should be fun for me to get back all those memories.. back then, i've made some complicated 3D drawing programs, image converters, and simple RPGs, this should help me along my journey!

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eblc1388

Here is some more information for you to start your project going.

Simple Logic Analyzer

The author had not provided the source(BCB6) code for the PC software but he did included the EXE instead. The ASM source of the AVR was there too.

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L.Chung

ikalogic

Thanks a lot, i've seen that a couple days ago.

My challenge is to build it with only an ATMEGA16.

There is some chances i could reach the 2 Mhz sampling rate he has achieved, or even cross it. I am using inline assemble codes for the critical sampling loops. the rest of the program is written in standard winAVR C.

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ikalogic

hello guys, here is what i've been up to, the hardware part is finished.. and guess what, I reached 3 MHz sampling rate with a 12MHz crystal, i could reach 4 MHz sampling rate with a 16Mhz crystal. I am actually storing 1000 samples before sending them to the PC.

I still didn't work on the triggering, but i don't worry about that part.

As for the the visual basic software that treat all this received data, here what i'll be getting into in the tomming weeks! (yes i work only the week-end since i started my summer training in that electronics company...)

One more detail, the whole is powered from the serial PORT, no need to external power. Also, it is actually connected to USB via a USB/SERIAL cable.

Attached Images

	P6080388.JPG (574.9 KB, 22 views)
	P6080396.JPG (633.8 KB, 19 views)

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Ibrahim Kamal
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gramo

Looking nice ika!

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Spency.

PIC Micro's - Your mind is the limit

PIC's and interfacing with other devices - a PIC Basic Guide @ digital-diy.net

ikalogic

here a snapshot on the progress in the software part... all the harsh math and timing calculations part is almost done, as well as the graphics part... still a couple days of work.. luckily it should be ready for the next week-end with the online help!

By the way, if anyone don't mind giving me a hand, i might need some beta testers for the software.. anyone? (all help will be credited to the helper, sure!)

Attached Images

screenshot.JPG (49.8 KB, 19 views)

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Ibrahim Kamal
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pc88

For viewing the signals, you might have your program work with GTKWave

ikalogic

good idea.. i might add an option to "export data GTK wave file"

So, ain't anybody interested in getting his hands dirty - just a little! - on that project with me?!

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3v0

Looks good so far. You are using the processor to store the data and do the triggering. The sampling rate will be reduced with triggering. Maybe not too much with simple triggers.

I can layout a PCB if you would like. Currently I am into PICs and do not have a AVR programmer so I can not create a working unit here.

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ikalogic

Oh well, if you'r interrested, I can give you all the required information for you to develop the same device but PIC based, using the same software.. actually i am putting a set of quite cool functions into that software, like duty cycle, average value and Frequency measurement, on all data or on selected periods. Also i am planing to do some SPI and UART signals decoding.

I would be very happy to work with someone experienced person on that project, and i believe we can develop a very useful while very cheap tool for the community.

About PCB, since i moved from Egypt to France for my studies, i don't have any of my PCB production tools, so i use strip boards instead..

By the way i have a question about triggering.. it seems i am misunderstanding something! I'll tell you what is my concept of triggering and you tell me if i am correct: Instead of directly starting to sample the inputs at the predefined sampling rate, the logic analyzer will wait for a certain condition to be met, like a falling/rising edge, or some bit configuration, then as soon as this configuration is met, sampling starts at the predefined sampling frequency, and stops when the 1000 samples are stored.

Am i right? Or should the trigger condition to be met for each and every sampled bit??!! that seems strange to me, because all the mesurment devices i've used uses the trigger to start sampling only.

3V0, that makes me confused, because as far as i understand, the trigerring may only delay the first sample, then, sampling rate is not affected since it is the same algorithm...

Please correct me if am wrong!

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3v0

I still may be interested. I have no idea what you code looks like please forgive me if I am off base.

Most of the time you are interested in seeing data on both sides of the trigger. To trigger you have to read the port, store the data, and do the trigger logic. You could sample at a higher rate after the trigger is meet but that would be odd.

Most people want to see data on both sides of the trigger so store/capture after trigger is a special case.

If you choose to not store data till after the trigger you could possible do simple triggers in the same time as the store opeation (which you are skipping here) and get the same sample rate pre and post trigger. If the trigger takes longer you may miss a sample or two following the trigger or even miss the trigger if an involved singnal is a short pulse. One you would catch at the post trigger sample rate but not the pre trigger.

After the current project is finished would you be interested on adding the SRAM and a FPGA? PIC with USB or AVR with USB?

I did not actually design LAs. I wrote firmware for LA probes.

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