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Old 14th April 2008, 09:56 PM   (permalink)
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I don't have multisim but I simulated the divide-by-five counter on Electronic Workbench. I found a couple problems on my simulation and I don't know whether they apply to your problems but you might check:

1. The standard clock generator model generated two clocks out of phase, i.e. the rising edge of the 1000Hz clock appeared on the following edge of the 500Hz clock. The two rising edges need to be coincident. I corrected that by generating the 500Hz clock from the 1000Hz using the 7474 FF connected as a divide-by-2 (connect D to Q').

2. My 74LS190 simulation model gave an incorrect RCO output. It should be only the width of the negative clock pulse, but it was equal to a whole clock pulse. I corrected that with an added OR gate. (This should only be needed if the simulation model is incorrect. The actual circuit should operate as stated.)

I corrected these errors and it appears to work properly, counting 5, 3, 2, 1, 0, 5, 4,... Attached is a view of the logic simulation.

TRACES
Top - 1000Hz Clock
2nd - 500Hz Clock
3rd - Counter QA Out
4th - Counter QB Out
5th - Counter QC Out
6th - Counter QD Out (Always 0)
7th - RCO Out
8th - D FF Out

Hope this Helps
Counter Out.JPG
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Old 15th April 2008, 02:11 AM   (permalink)
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I'll give that a try and see if it works in multisim.
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Old 15th April 2008, 06:17 PM   (permalink)
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So are you saying to use 2 FF, one to cut the time in half and the other to control the div counting?
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Old 15th April 2008, 07:03 PM   (permalink)
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Quote:
Originally Posted by chelm
So are you saying to use 2 FF, one to cut the time in half and the other to control the div counting?
Yes. I did that because the clocks provided by my simulator were not the phase I needed.

P.S. I noticed in my schematic that the 7474 was not grounded. Pin 7 should go to ground.
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Old 15th April 2008, 07:45 PM   (permalink)
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So I should use the output of the FF that cuts the clock in half to go into the CLK input of the second FF for div counting right? Could I use the output of the FF that cuts the time in half on all of the DIV counters? Or should I have a different one for each div counter? So I know I have to cut the time in half for the tens of seconds, but do I need to cut it in half again for the tens of minutes?
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Old 15th April 2008, 09:55 PM   (permalink)
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I may have completely miss understood what you were saying, but I think I wired this the way you suggested.

I'm having 2 problems now, first it counts down from 59-9-59-50-59-50-49-9
it's also decrementing the minutes on the second 59 count, it's just strange.

(I only modified the counter for tenths of seconds)
Attached Images
File Type: jpg clock30.jpg (207.1 KB, 2 views)
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Old 15th April 2008, 10:33 PM   (permalink)
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Quote:
Originally Posted by chelm
I'm having 2 problems now, first it counts down from 59-9-59-50-59-50-49-9
it's also decrementing the minutes on the second 59 count, it's just strange.

(I only modified the counter for tenths of seconds)
I don't understand tenths of seconds. Aren't you counting seconds in the right display?

You did the clocks backwards. If you look at my circuit the high frequency goes to the load FF (U17 in your circuit) and the divide-by-2 frequency goes to the counter.

-----------------------------

I used to be fast and sloppy. But now that I'm getting older, I'm losing my speed.
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Old 16th April 2008, 01:20 PM   (permalink)
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Yes I misspoke, or mis-wrote rather. Tens of seconds is what I meant, sorry. I'll take a closer look at this, I thought I had it setup the same way you did. I apologize if I missed something.
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Old 16th April 2008, 01:42 PM   (permalink)
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So I connected it like this: I think this is what you meant, but now they count independently. The seconds count like this: 59-50-59-50-49-40-49-40-39-30-39-30-29...
Attached Images
File Type: jpg clock31.jpg (202.0 KB, 4 views)
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Old 16th April 2008, 04:41 PM   (permalink)
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Sorry, I wasn't more clear.
The divide-by-2 FF clock is now your main 1 second clock and goes to all the counters. The undivided clock goes only to the carry FF's.
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