Hi Eric,
That's a good idea about the graphical monitoring I'll try it and see if I can get a better handle on things. I wrote a program in the past to generate a frequency through the parallel port using the QueryPerformance functions for timing in order to test another circuit I had built. For this I set the program to real-time mode in the task manager to disable any Windows interrupts and get a stable output.
I tried to find some practical information about the use of the ADC on the internet and came across this page: http://www.emesys.com/OL2tlc2543.htm.
They use the Basic Stamp microcontroller to control the TLC2543. Towards the bottom of the page they give a bit of information about things to be aware of in order to ensure stable operation, some of which is a tad beyond my understanding. I'd be grateful if you could have a quick look and see if there is anything there that might important enough that I should be considering in my own circuit.

Thanks,
Salvatore.

 

hi,
Towards the bottom of the page they give a bit of information about things to be aware of in order to ensure stable operation, some of which is a tad beyond my understanding. I'd be grateful if you could have a quick look and see if there is anything there that might important enough that I should be considering in my own circuit.

This refers to source impedance of the Analog inputs, all it means is that if the source impedance/resistance is too high,
the internal 60pF capacitor inside the ADC ic will not be able to charge/discharge fast enough via this source resistance,
before the ADC conversion cycle starts.
This would mean an error in the ADC value, they are suggesting hanging a large cap [0.33uF] on the ADC input,
this cap would transfer some of its charge to the 60pF, which would make the error due to a high resistance source smaller.

Its best to stay within the datasheet spec for the source impedance for optimum accuarcy.

Lets know how you get on, others may benefit from your work.

Regards

__________________
Eric
"Good enough is Perfect"

PIC tutorials:
Gramo's: www.digital-diy.net/
Bill's: www.blueroomelectronics.com/

 

I'll certainly keep you informed if I make any discoveries. Thanks for your input!

Salvatore.

 

hi,
Attached zip file, basics of a graphical display for the ADC port.
I have tested it using a 4013 dual bistable as the ADC ic and it works OK.

The MakeAry subr has also been modified.

Regards

Attached Files

Salv2.ZIP (6.6 KB, 7 views)

 

hi salvatore.
Upgraded zip, you should find this version easier to modify for your trials.

The sample graphs are produced by the 'clock' driving a 4013, connected as a divider.
Regards

Attached Images

Image4.gif (29.5 KB, 16 views)

Attached Files

Salv2a.ZIP (39.4 KB, 3 views)

 

Hi Eric,
Thanks for sticking with it, much appreciated! Your programs confirm the readings I'm getting, for an input of 0V the readings are clearly around this value, the same for an input of 5V. For each voltage input the results are actually not totally random but form part of a set of values. I did some graphing of the readings as you suggested and some interesting results were thrown up. I've combined the results into a single graph ( see attached ). For each voltage input ranging from 0V to 5V in steps of 0.25V, I took 100 readings and plotted them on their own graph along the x-axis. There is some sort of transition around an input of 2.5V. I don't know what these results are an indication of. I've searched the internet for example circuits utilising the 2543 and it seems to be a popular IC for ADC conversion, but I haven't as yet come across any mention of this particular problem. There are suggestions as to how to wire the 2543 up in terms of seperate grounding of the analogue, digital and power supplies in order to minimise errors, but I gather that this is to ensure full potential accuracy as opposed to overcoming seriously bad readings. I'm going to re-arrange the grounding and see if this makes any difference...

Thanks,
Salvatore.

Attached Images

Graphs.jpg (218.2 KB, 13 views)

 

hi salvatore,
Looking at your drawing, you have not shown a 0V gnd connection from the parallel port Pin18 thru 25, to the external power 0V gnd line???

Is this a dwg error?

 

Hi Eric,
Yes, that is an error or rather an omission, I have pin 25 as the ground. I've done some further analysis. I've used the DAC to supply a range of input voltages to the ADC from 0V to 5V in steps of 20mV. For each voltage input I took 100 sample readings and averaged them. I plotted these average readings on a graph, with input voltages along the x-axis and averaged ADC readings along the y-axis ( see attached graph ). The results are very consistent from run to run. I've changed the grounding but the result are the same.

Salvatore.

Attached Images

Graph2.jpg (114.5 KB, 8 views)

 

Hi Salvatore,
Have looked thru your results graph.

Is it possible that you could post a copy of your latest program?

On your original program in the first address sequence, where you had the copy/paste error, are you still switching Dta2 CS line, on the D9 clock cycle??
If so, you are resetting the ADC's internal counters and all your sampling will be out of sequence. This could account for the 'repeatable error' in the results.
Regards
Eric

 

Hi Eric,
I've attached some files that contitute the source code and the installation package. I had to do a major tidy up on the code as it was starting to get messy with all the quick and dirty test code that was added..! I had to split the installation package into 5 pieces as I couldn't upload in a single .zip file ( the upload size for a .zip says 9.54MB but anything over 1MB fails..? ). Unzip all the Package files into one folder ( discard the .txt files ). Run setup.exe to install the program, controls, etc. You should then be able to view the source code in full. Let me know if you have any problems..!

Thanks,
Salvatore.

Attached Files

	Source.zip (11.5 KB, 2 views)
	Package1.zip (66.6 KB, 2 views)
	Package2.zip (563.6 KB, 2 views)
	Package3.zip (706.0 KB, 2 views)
	Package4.zip (707.1 KB, 2 views)
	Package5.zip (429.3 KB, 2 views)

 

hi,
Downloaded the zips, unpacked OK.
Program runs as *.exe and in VB design time OK.

Using the 4013 test jig, the ADC results are correct???

I will do more work on the program tomorrow.

Regards

 

Hi Eric,
Guess what? I found out what the problem was... the DB25 printer cable I was using..! Doh! In order to test if the software worked on another machine, I downloaded the software to a laptop, connected the printer cable as normal and I got exactly the same rubbish results. But because I could get the laptop very close to the circuit I decided to remove the cable and plugged the circuit's DB25 male connecter straight onto the laptops parallel port, and hey presto, a straight line graph..! Analysing individual ADC reads, the 5 LSB's are a tad random meaning a 32/4096=0.0078% error at full scale. This is still pretty good for my purposes but I know the ADC is capable of better. This is more than likely the inputs and/or the way the circuit is laid out so a bit of work to do there. This also begs the question about the cable itself. Clearly it is only the DATAOUT line that is getting corrupted because the other lines are working well enough to drive the DAC with no problems. As an experiment I'm going to change the DATAOUT line for use with another status pin and see what result I get. It may be that he cable itself is at fault I'll have to see. Any how, after all that banging my head against a brick wall the mystery is finally solved..phew..! Thanks for all of your help, it certainly kept me going!

Thanks,
Salvatore.

 

32/4096 is 0.0078 which is 0.78%.

 

Oooops.. ! Yes, thanks for the correction..!

 

Hi Salvatore,
Pleased to hear you are making good progress.

I have found that the 'makeup' of parallel cables can vary quiet a lot.
Some have a data wire twisted with a dedicated 0V wire, others rely on a overall outer screening, some dont have all the 0V's, pins 18 thru 25 connected.

Also the length of the para cable should be as short as possibe, the pulse edges become degraded, some homemade para programmers can suffer from this problem. It is possible to fit non-inverting buffers on the data lines if its necessary to have a longer cable.

Regards
Eric