I am trying to accomplish the following:

I have a laser that outputs a sync signal from a photodiode in the cavity at 82 MHz. The signal is TTL, I think about 2 ns in width. I have a digital I/O PCI card that I would like to gate on this photodiode signal. The problem is that the card can only be gated up to 2.5 MHz.

We can just work at 2.5 MHz gating, and ignore all of the other events, provided that we can just divide down the 82 MHz input. The division should be rather accurate, so that we can continue to gate accurately despite any phase shifts in the sync signal.

I have had trouble finding IC frequency dividers that work in this frequency and voltage range (output a 4-5 V signal that we need for gating). Can anyone suggest an IC or other solution?

 

You might start by explaining the connection between 2 nanoseconds and 82 mHz., because I don't think there is one. Second, I have no idea what you are talking about when you say "I have a digital I/O PCI card that I would like to gate on this photodiode signal."

Do you want to use the pulse with a 2 ns width to create a pulse that is 400 ns wide with the leading edges a fixed delay apart? That's the best I could come up with from your description.

A timing diagram would be a big help.

 

There isn't a direct connection. There is a pulse train of 2 ns pulses with the rising edges of each pulse separated by about 12 ns (that comes from the 82 MHz repetition rate). I'm not too concerned about the width of the output pulses as long as they come at a rep rate of 2.5 MHz or lower.

Maybe "trigger" is a better word than "gate." The PCI card takes in digital signals and has a REQ channel which can be used to trigger data collection. The reduced frequency output from the circuit I want to build will be sent to this REQ channel.

Spreading of the pulse width due to frequency division should be acceptable. That takes my 2 ns input to about 80 ns if I divide by 40. The spacing between the rising edges of each pulse should then be the reciprocal of the input frequency/ 40 or approx. 500 ns.

 

Right - now I see the picture.
74F series flip-flops will not work in this application because the clock high and low times are in the 5 ns region
74AC series flip-flops have a typical clock pulse width requirement of 2.5 ns. That's tantalizingly close but no cigar.

This flip-flop may work for you
http://www.fairchildsemi.com/ds/NC/NC7SZ74.pdf

This will then allow you to use a counter for the rest of the job.

 

Hi Erglion,

Here's another one, again no guarantee that it will work.

http://www.alldatasheet.com/view.jsp?Searchword=74ABT74

I wonder why they would equip it with a TTL output if no TTL
IC is fast enough ? What's the amplitude of the
pulse ? Could you upload a screenshot of the scope ?

on1aag.

 

Okay, I'd moved away from this problem for a week, but now I'm back on it.

I was mistaken about the characteristics of the input signal I'm trying to divide. It is, in fact, a square wave with a period of about 12 ns (6ns high, 6 ns low with rise/fall times ≤ 1 ns). The amplitude is 1 V. I'll attach a scope screenshot since I'm having some trouble uploading to the web from work.

Attached Images

monitor.JPG (57.5 KB, 32 views)

 

Probe setup at 1x, 4div@200mV/div.
That was small signal, right?
If that was fixed frequency signal, you may used IF mode. It's about mix it and select it with filters to get IF frequency. This method was applied to most analog radio communication. So, that was many references available.

 

Looks like he had the input impedance set for 50 ohms, which loads the crap out of the signal. I would switch probe impedance to 1Meg and try again. Scope input capacitance might then be a problem, however.

__________________
Ron

 

hi,
The best action would be to connect a 74F74 or 74AC74 to the signal and see if it divides the signal.

Regards

__________________
Eric
"Good enough is Perfect"

PIC tutorials:
Gramo's: www.digital-diy.net/
Bill's: www.blueroomelectronics.com/

 

Yeah, its the scope capacitance--I've noticed this before. Not too worried about it in this case, but thanks.

Thanks. I'll look into this and let you know how it turns out.

 

My point was, your signal amplitude is probably much higher than the ~1V p-p shown in the scope photo. It is probably TTL levels, as you originally stated.

__________________
Ron

 

I've been working on this on-and-off, and I've learned a lot, but now I'm stuck again.

My current setup has an amp (MiniCircuits ZHL-1000VH) to bring the 800 mV p-p input up to TTL levels. Then I synchronously divide the 80 MHz to 20 MHz using 2 JK flip-flops (74F107). Next I connect to a 4 bit counter programmed to divide by 10 (74F163). This gets me the desired divide-by-40 circuit, and it multiplies the period by 8 times (also desired).

The attachment shows the divider input in yellow, output in blue.

My current problem is cleaning up the output. I'm particularly bothered by the noise on the top of the HI signal. For this I've tried using a comparator (LM361) with a Vref around 1.2V, but the output looks the same.

Other ideas I had are (1) filtering (2) locking to a PLL to produce a clean signal, or using a PLL divider like ADF4007 (3) using a different amp or a fast comparator for the input signal, since the divider works fine when I drive it with a function generator.

Any suggestions are greatly appreciated.

Attached Images

divide_by_40.JPG (56.7 KB, 17 views)

 

If channel 2 is the output of the 74F163, then the culprit could be that you do not have adequate supply bypassing on the TTL IC's. This would explain why the output of the comparator is not any better also. Do you have a 0.1uF cap across each of the 74Fxxx chips?
The other issue is that you are still using the 50hm: input on your scopes channel 2! Also, for fast rise signals it is generally better to use a X10 probe because these have less capacitance and better frequency response.

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Thanks for the suggestion kchriste.

I have limited electronics experience, but I assume that when you say "supply bypassing" that means I should run those capacitors between V+ and GND before each of the ICs. Previously I had only one 1 nF cap in there, but I put in two .1 uF caps, one before each IC. This actually didn't change the output at all. More surprisingly when I looked at the supply line there was definitely some 80 MHz pickup (regardless of the .1 uF caps) [see attachement]. Some of this was just from the probe, but a substantial amount remained.

I'm starting to think that the pickup might be the biggest issue I'm facing. Even if I monitor other circuits on the same breadboard that are independent of the rf signal they show appreciable pickup.

Regarding the 50 hm: probes, those channels were measured using test clamps attached to RG-58 coax, which I thought was fine. The other channel was measured with a standard 1 Mhm:, 10x probe. I found a second 10x probe, so I'll just use these in the future. The screenshot I posted earlier looks essentially the same except that the edges of the tall peaks are a little more square.

Attached Images

ac pickup.JPG (50.0 KB, 7 views)

 

I mean as close as possible to the V+ and GND pins of each chip.
Breadboards are really bad for high frequency circuits because of the high inductance of the connections and high capacitance between them. Not to mention the lack of a ground plane. This is most likely the source of your problem.
One way to reduce pickup via the ground connection on a probe is to use a.... I forget the name of it, but basically it is a short connection from the ground ring at the probe tip to the ground on the circuit under test. It looks like a tightly wound spring with the end of the coil unfurled and sharpened for good contact. The "coil" part slips over the ground ring at the probe tip thus making contact to the probe. The idea is to use as short of a ground connection as possible.

__________________
--- The days of the digital watch are numbered. ---