Well for the D/A i am using a R2R ladder with R=10k . As far as the OR gate i am using a SN7432N, is that ok ?
I think the guess by the d/A is off because its not taking into account the other 4 bits.

pete

 

The TTL logic high level of the 7432 may be too low for your 74C905. Try adding a 10k pullup from the 7432 output to +5V.
As I mentioned in a previous post, you will need either a commercially available R2R ladder, or 0.25% (or better) resistors if you make it from discrete resistors. Otherwise, it will be nonmonotonic. Also, the ON resistance of the Q outputs is about 200 ohms typical, 350 ohms max. This resistance adds to the value of the 2R resistors in your ladder, which causes additional error.
The unused bits will only cause quantization error, which for 8 bits is 5V/2^8, or about 20mV.

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Ron (aka Rube)

 

So what exactly in the schematic is the function of the OR gate in this application ?

Pete

 

According to the datasheet,

Quote:

If the register is truncated and operated in the continuous conversion mode, a lock-up condition may occur on power- ON. This situation can be overcome by making the START input the “OR” function of CC and the appropriate register output.

I looked at the truth table to try to understand this, but I still don't. It looks to me like you would need a minus OR (AND) for this function. If no one else here explains why it is an OR on the datasheet, you might want to try a 74HC08 or a CD4081 (quad 2-input AND gates). These have logic levels compatible with your SAR.

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Ron (aka Rube)

 

I will try using the AND gate later on today, thanks for the suggestion...I will let you know of any observations..

The way i have it running now is by connecting the /cc to /s, what negative effects would that have ?

Thanks for all your help by the way Ron.
pete

 

I already answered this question in my previous post (or rather, the datasheet answered it). I like helping people, but carefully reading each post is important.

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Ron (aka Rube)

 

I was just re asking differently because its sometimes hard to decipher spec sheets.

Anyways, first i tried replacing the 7432 IC with another to make sure the same thing would happen and indeed it did. I then proceeded to place a pull up resistor on the output of the OR gate and that really didn't change much. My next change was to replace the OR gate with an AND gate specifically an 7408 IC. Interestingly this actually yielded some decent results, At zero input volts the serial out yielded a straight line at level zero while turning the pot yielded various waves.
To further test things i also replaced the resistors with more accurate metal oxide type ones and the results where pretty decent and improved. One slight issue is the highest analog input voltage its willing to display digitally is 4.35V . Anything more than that and it just goes all HIGH. Not sure whats the deal with that.

THanks
pete

 

Any new ideas on the low voltage thing ?

Also RON if you can possibly help me out with the circuit to replace the LM311, i would highly appreciate it.

Thanks
pete

 

4.35/5 ~ 7/8. A 3 bit converter with a 5.000V reference would have 4.375 as the maximum output. If the reference were 4.971V, a 3 bit converter would have 4.35V as the maximum readout. Are you sure you are getting all 8 bits to your display? Or maybe you only have a 3 bit converter. Are you feeding pin 7 back to the AND gate? I noticed that if the opposite pin (18) were fed back by accident, you would have a 3-bit converter.
Sit down before you look at the comparator schematic. This works well in simulation. Offset voltage can be a problem with discrete transistor comparators. You can either live with it, or you can match them in pairs - Q1 and Q2, Q12 and Q13. You should use 1% resistors for R5 and R6.

Attached Images

comparator.PNG (30.7 KB, 54 views)

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Ron (aka Rube)

 

I have verified the circuit and indeed all 8 bits are connected correctly. Pin 7 (Q3) goes to the and gate and not 18. I have made some voltage measurments, maybe they can aid in some speculation of the problem.

Analog IN ... D/A Out AND Gate ... D/A Out Direct /S to /CC
.20 ...... .61 ..... .46
1.26 ..... 1.26 ..... 1.25
2.0 ..... 2.01 ..... 2.04
2.5 ...... 2.23 ..... 2.3
3.5 ...... 3.69 ..... 3.68
4.25 ...... 4.11 ..... 4.17
5 ..... 4.39 ..... 4.56

+5Volt Regulator OUT : 5.00 volts
-5Volt Out : -4.78 volts
+12volts Supply: 11.93 volts

Anything look odd ? Ideas ...

pete

 

Do you have plenty of power supply decoupling caps, and good ground planes? You should have, at minimum, a 100nF cap from each supply pin to GND on each IC (or circuit, when you go discrete). The fact that you get different answers with and without the AND gate implies to me that you need better decoupling and/or a pullup on your AND gate output (or a CMOS AND gate). Re-read my comments about logic levels.
Your LSB is only 20mV. Digital noise can easily be 10 times this. It is best to have separate analog and digital ground planes, with them connected to each other at one point only. I don't think this will work in the case where you are using the SAR outputs as the switches for the ladder network.
Since you are also using +5V for analog and digital purposes, you need to be sure that +5V is extremely clean (well-filtered/decoupled). It is the reference for your A/D and for your D/A.
From a noise standpoint, it would be better to have a separate analog +5V, with a D/A which does not use the outputs of the SAR as the switches for the ladder network, because the SAR puts a lot of undesirable current transients on the +5V supply.

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Ron (aka Rube)

 

Hey Roff i got around to building the circuit and something isnt working right. Input transistor one gets very warm and regardless of the input state the output is 5 volts ?
Any ideas where i can look to fix the problem ?

Thanks
pete

 

What type of transistors did you use? Did you make any assumptions about the pinouts on them?

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Ron (aka Rube)

 

You wont believe the stupid mistake i made ....lol
I assumed that the transistors are the common EBC pin variety so when i connected it all together nothing worked. Yesterday night it hit me to check everything and look at the data sheets and then i realized they aren't the normal pinout but rather BEC. I will try that today..

Can u please explain the purpose of the diodes ? Also in brief the purpose of the different stages...I recognize the first stage as being a diff amp...

Thanks
pete

 

I believe it. That's why I asked the question. Don't feel like the Lone Ranger.
D1 and D2 keep Q1 and Q2 out of saturation (saturation takes time to recover from). They also limit the signal swing into the second diff amp, allow it to fully switch (with large-signal inputs), but minimizing the overdrive recovery time that would be required if they were absent. They add unwanted capacitance, so small-signal Schottkys (with low capacitance) were specified. D3 keeps Q10 out of saturation, and also limits the overdrive recovery time at the base of Q11, by clamping the swing to +0.7/-0.4V.
Overdrive recovery time is a function of the current available to charge and discharge the capacitance of a node, and the voltage over which that node must move before switching occurs.
EDIT: Below is an annotated schematic.

Attached Images

comparator annotated.PNG (42.0 KB, 22 views)

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Ron (aka Rube)