vhdl programming - Electronic Circuits Projects Diagrams Free

abilash · 7th February 2007, 08:25 AM

i am doing a project in vhdl. i am using xilinx6.1 and modelsim for simulation purpose. i need to divide the project into modules. i would like to know how to link one module to the other module so that the whole work together. please do help me with this.
thanx a lot

with regards....

hjames · 7th February 2007, 03:25 PM

Create a new vhdl module, then declare and instantiate it in the main module.

Go download the webpack 8 or 9 and look at the help files in there. (Under the edit > language templates) menu, or dig around in the xilinx 'XST' references.

The manuals are online, use them.

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7th February 2007, 08:25 AM	(permalink)
abilash	vhdl programming i am doing a project in vhdl. i am using xilinx6.1 and modelsim for simulation purpose. i need to divide the project into modules. i would like to know how to link one module to the other module so that the whole work together. please do help me with this. thanx a lot with regards....

7th February 2007, 03:25 PM	(permalink)
hjames	Create a new vhdl module, then declare and instantiate it in the main module. Go download the webpack 8 or 9 and look at the help files in there. (Under the edit > language templates) menu, or dig around in the xilinx 'XST' references. The manuals are online, use them.