Well i eventually made it work, somewhat. But once it gets latched it doesn't get unlatched. Any way 2 make this circuit act as atoggle switch?
Well, i built this circuit(see attachment) to be used in a switching application. I used the same values of components as given in the schematic except the Electrolytic cap--i used 1uF instead of 0.1uF coz i had that by me then. Vcc in my case is about 8.4V. The problem is that the output pin is always at a Pd of 0V across Ground 8.5V across Vcc--even after pressing the switch. Please help
Well i eventually made it work, somewhat. But once it gets latched it doesn't get unlatched. Any way 2 make this circuit act as atoggle switch?
Someone posted this a while back, it can easily be used as a digital toggle.
The RC network on the clock input is necessary to debounce the switch. Otherwise, the flip-flop will toggle several times each time you depress the switch.Originally Posted by apakhira
Here's the rub - some mfrs (Philips, maybe others) have a Schmitt trigger on the clock input, so the clock is insensitive to transition times. Unfortunately, others (ON Semi, National, Fairchild, ...?) do not use Schmitt trigger clock inputs, and the specified maximum risetimes are around 5 - 10 microseconds. With the posted schematic, the risetime will be around 20 milliseconds. If you used 1uF, it will be 200 milliseconds!
As I said, you have to have some sort of clock debouncing. You can do this separately with an additional circuit, get an HEF4013 from Philips, try to find a Schmitt CD4013 from another mfr, or use another scheme which is insensitive to switch bounce.
Fine. I tried holding the switch pressed 4 a whole second. It switches on fine. But then the damn output(Q) refuses 2 change back to 0. Why?
And do u mean i can't have rebouncing just with an RC network.
Could u also post the formula u used 2 calculate the rise time 4 network? How about if i use a 0.01uF non-polarized cap--will that work better?
How will very small cap values affect the thing?
and about my problem?(not going to 0 state)?
Ron H explained the reason in his first post. I quote "Here's the rub - some mfrs (Philips, maybe others) have a Schmitt trigger on the clock input, so the clock is insensitive to transition times. Unfortunately, others (ON Semi, National, Fairchild, ...?) do not use Schmitt trigger clock inputs ....."Originally Posted by apakhira
As he said later, you need to either buy a Flip Flop that has a Schmitt trigger in the Clk input circuitry, or use the one you have but insert an external Schmitt Trigger package such as the 40106, 74C14, etc.
Also, I notice that there is no bypass capacitor shown on your circuit. You should use a 100 nF ceramic across the Vss to Vdd. Otherwise you could see strange behaviour.
Len
But i think he also said that the RC network will do. Well, anyway, i have something 2 say about the RC network. See if u can explain them:
1. When i disconnect the cap, i can switch on and off normally, but there is the bouncing problem (switches on after many tries)
2. But when ithe cap is disconnected it switches off in just one press of the button. Thats no coincidence. But why?
3. When the cap is connected it switches on in one try but never switches off, even tho Vcc is going into pin when i press switch..
Why r these happening?
There is something internal to the design of the flip-flop that allows it to toggle high but not low when the clock risetime is slow. Are you just trying to understand why it works this way? You would have to have a schematic (which may be in the datasheet) and understand CMOS circuit design to understand this. If you are just trying to build a toggle FF, accept the fact that it won't work the way it is, and get on with life. You are whipping a dead horse, as far as I'm concerned.Originally Posted by apakhira
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