I am having a couple of problems with my clock circuit can any one help?

I am have to using the following IC chips: (kind of fried the last batch)

7493 Binary counter
7447 BCD to 7-Segment Decoder/Driver
7 Segment Displays

Problem:
1.) I have created this section of a 12-hour clock. The ONEs HOUR section counts 0-12 I only want it to count 1-12. What do I have to do to alter this drawing so that it will count 1-12?

( The funny c, backwards c, and the top of a four shapes)
2.) The count sequences counts 0 1 2 3 4 5 6 7 8 9 [ ] u . After making the sequence not count the zero I want to get the count to count 1 2 3 4 5 6 7 8 9 0 1 2 instead of the shape how can I do this?

3.) Next I have to run the ONEs HOUR to the TENs HOUR and connect them so that the LED turns on and only shows 1 when the other counter counts 0 1 2 (which means ten, eleven, & twelve) after the 1 2 3 4 5 6 7 8 9 count. What can I do?

Please help, if you can with any of these problems I am having.
Thanks.

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If you use a 7492 things get easier, since it can be used modulo 12.
Truth table. The A B C D are the outputs of the 92 and A'B'C'D' are the required outputs. The bits that must be changed are in bold. There are two states to detect, 10/11 (B and C) and zero (norABCD). The tens output can be obtained by OR these two states.

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The '92 doesn't count like that. It does not go consecutively like the '90 or '93. It has six MSB low, and six MSB high. Q0 is fine, its output is consistent with the pattern we want. Q1, Q2, and Q3 must be corrected, like I mentioned in the thread with a similar name the other day. Using a '93 allows all of the patterns to be right, with the slight correction of turning 0 to 12, and having the counter reset when it gets to 12. Either way, there is going to have to be some logic correction. I'm assuming he doesn't know how to do logic minimization with K-maps and things. I shall try it tomorrow when I have more time. IlordrossI, until then, search for a good write-up on Karnaugh Maps.

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Ok, here we go with a '93. When I say something like D3 = (Q3 /Q1) that means you're putting Q1 into an inverter, then AND'ing that with Q3. The output of that AND gate will then feed into your seven segment decorder 7447's D3 input. It might be helpful to go through this same method with a '92. The logic gates might be more, or they might be less, as you wouldn't need an additional gate to handle the reset. Try it out.

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I had assumed (incorrectly) that the 92 was an extension of the 90, but I see now that count "3" in the ÷ 6 section is skipped. A 93 with C and D connected to the MR inputs will give the sequence.