Does anyone know of a dual channel 3-input OR gate? I can only find a NOR version but need it on a single chip (no external inverters...though I suppose I could connect it to a 2 channel inverter) because matching is critical.

Or anything else that will allow digital lines A, B, and C to drive line D with a HI being dominant over a LO. But I need to prevent the signals on ABCD from travelling backwards to the sources driving either A, B, or C. Kind of like a one-way merge road, like a diode but no voltage drop or current requirements.

 

You may try the CD4072 (dual 4-input OR gate) or the CD4075 (triple 3-input OR gate).

 

Search Results
DUAL 3-INPUT OR

10610/BEBJC IC LOGIC GATE DUAL 3-INPUT OR ECL10 DIP 16PIN CERAMIC

100102A 3-Input OR-Function Logic Gate

74HC4075N Triple 3-input OR Gate

CD4075BE CMOS TRIPLE 3-INPUT OR GATE

CD74HC4075E HIGH SPEED CMOS LOGIC TRIPLE 3-INPUT OR GATES

MC10110L Dual 3-input/3-output OR Gate

http://store.americanmicrosemiconduc...r-3-input.html

· 100102A
· 10610/BEBJC
· 74HC4075N
· CD4075BCN
· CD4075BE
· CD4075BFX
· CD74HC4075E
· MC10110L
· MC10110P
· MC10210FN
· MC10210L
· MC10H210L
· MC10H210P
· MC356G
· SN74HC4075N
· SN74LS154N
· TC4075BP

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John DeRosa (Hotwaterwizard)

hotwaterwizard@aol.com

 

Thanks. I've gotten rid of some needless parts so I don't need a dual OR anymore so it's easy enough to find a single channel 3-input OR.

DOes anyone know if such a thing as a D flip flop with a "bypass" exists? I don't think I can just bypass it with a MOSFET to short across the input and output since that will produce a short if the line is high while the DFF is trying to pull the output low.

 

Do you want something other than a latch - the predecessor to flip-flops? The 573 octal parts are pretty common. When enabled, they pass the input to output, when disabled, they hold the last output value.

 

A latch might do the job, but I think what you want is a multiplexer. Run the input to the flip-flop and the output to the A and B inputs of the mux. Use the select line to choose from among the alternatives. You can implement the mux with gates if you like. Assume D is the input to the flip-flop and Q is the output. Then if S is the select line and M is the multiplexer output you have
You could also build this from an analog switch with one NO and one NC contact activated by the same select line.

A transparent latch and a flip-flop are different animals with respect to the system clock. You should exercise some care if you go this way.

 

I don't think it's a latch I need. Under certain conditions the data is only valid on the rising edge and any stray data that gets passed to the output other than the data on the rising edge will confuse the uC. Hence the D-FF, and not the latch since there is a transparency that occurs.

But under other conditions the data is valid all the time and I need to "remove" the D-FF fromt he circuit, hence the bypass.

What I need is essentially a mux that the D-FF feeds into, but in my case I could just run an extra line from the D-FF input to the microcontroller rather than add a mux and additonal propogation delay.

 

Well, how fast are the signals you're dealing with? Using discrete logic like this with a uC is odd. The only times I'd imagine that it is necessary is if the signals are exceptionally fast, or you have some very hard timing requirements.

 

It's for back EMF zero cross sensing of a brushless motor. The back EMF will be sampled synchronously with the PWM during the PWM off-time. It can only be sampled when the high side FETs are off (low side is simply held on). THe same PWM signal that turns on the FETs will trigger the D-flip flop that will pass the output from the BEMF sampling comparator to the uC only on the rising edge of the PWM (while the high-side switches are off). Therefore, the sampling has to finish before the high-side FET starts to turn on (50ns- the propogation delay of the driver, the FET itself will take 23ns to ramp up). The PWM is 50kHz.

The D-FF does not allow the Back EMF to be sampled in the absence of the PWM driving the high-side FETs (again the low-side fets are simply held on), therefore I cannot sample the PWM when the robot is coasting or in any other situation where I want to passively track motion. That's why I want to be able to bypass the D-FF in those situations.

 

you are welcome.

__________________
John DeRosa (Hotwaterwizard)

hotwaterwizard@aol.com

 

Why not put the clock for the D-flip flop though a AND or an OR gate depending on your logic polarity? Then feed the PWM signal into one terminal of the gate and connect the other terminal of the gate to your uC so the D-flip flop can be triggered by both sources? Like this:

Attached Thumbnails

 

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Inside every little problem, is a big problem trying to get out.

 

Don't you mean an OR gate?

That's actually my preferred choice, except that I kind of wanted to use logic gates all from the same series...you know...just because.

THere is actually already a 3-input AND feeding into the D-FF since the D-FF is actually triggered on any rising edge of any of the three high-side MOSFETs). I would need a 4-input OR which doesn't exist for the series, but then it gets all into semantics of wanting to use logic gates from the same series.

UPDATE: So I found another series of logic ICs to pick from, one of them being an ECL 4-input OR gate. THanks!

EDIT: Bah the ECL thresholds are too close together and aren't quite compatible with CMOS. Maybe I just suck at hunting down logic gates but the only CMOS 4-input single-channel OR I can find is from TI, the CD4072B but the 60ns propogation is too long.

 

If the trigger signal normally low when inactive, then yes.... If it is normally high when inactive, then the AND gate is the solution.
What about the 74hc4072? It should have a shorter propagation delay time. Somewhere around 10 - 15 ns I would think.

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Inside every little problem, is a big problem trying to get out.

 

Is there a single version of it? I said earlier that I simplified the design and got rid of some things (dual is onyl needed if I can also sample the BEMF when the high-side is being held on and the low-side is being PWM'd, but due to comparator bias issues, I cannot).