Did anyone else see the new "Propeller" chip over at parallax? - Electronic Circuits Projects Diagrams Free

hjames · 2nd September 2006, 04:08 PM

Had me grinning the whole time I was reading through the data sheet. The most notable points:

8 "cogs" (i.e. cores)
80MHz operation (with a /4 - ~20MHz instruction rate unfortunately)
32 bit instructions
512 x32 words instruction/data memory per cog
8K x32 shared memory per chip
a rom table with a built in character font(complete with some electronic symbols ?!)

Looks like Parallax actually went and built the successor to the SX series of chips.

James

dknguyen · 2nd September 2006, 06:03 PM

Yeah. I am not sure what the point is of the cogs? Is it for some kind of parallel processing? To make it more convenient?

hjames · 2nd September 2006, 08:13 PM

The idea is to have less dedicated peripherals and let each cog be an "intelligent" peripheral. Each cog could probably implement a couple serial channels, spi, rs232, or whatever protocol, or generate a video signal, or just do general processing. This one chip could probably generate multiple video streams simultaneously...

Say you want to create a jitter free RC servo signal - a cog could probably generate a couple servo's worth of signals just sitting there in a tight loop counting clock cycles and doing nothing else. Then for the interface, you have another cog bit-banging the UART and doing all the slow and complex command parsing.

This chip is just too different from standard approaches to be "practical" in most applications, but from the hobby perspective, this is a really amazing chip/approach.

dknguyen · 2nd September 2006, 08:29 PM

Can you say robot arm?

hjames · 2nd September 2006, 08:42 PM

I grabbed one of the eval kits even though I'm pretty sure I won't have enough time to properly dedicate to it. It's just so amazingly close to some of the approaches I wanted to try when I first started using FPGAs.

It's the ultimate in distributed processing. Emulating neural nets or having each cog emulate a couple dozen interacting state machines would be so easy to try out on this thing. Throw a couple chips together and you can have as many interacting behaviours and control inputs/outputs as you would ever want.

Unfortunately the chips are really expensive, but if they drop the price a bit, I can imagine a board with a handful of these chips along with some CPLDs to route signals between chips... wow. Can you say "sea of processors"?

Someone Electro · 3rd September 2006, 07:51 AM

You can still take multiple MCUs and link them togetter by I2C or SPI

dknguyen · 3rd September 2006, 07:54 AM

Quote:

Originally Posted by Someone Electro

You can still take multiple MCUs and link them togetter by I2C or SPI

THat's what I'd do...with a CAN bus! (or SPI).

hjames · 3rd September 2006, 11:12 AM

The trick here is that the cogs are all implemented in ram - a single 512 word memory holds all the program and data code. Self modifying code and runtime code uploads/downloads would be the new tricks you can use with this chip.

Essentially it would be possible to reallocate processor resources when you need them - or time multiplex them if it's fast enough.

**Jay.slovak** · 4th September 2006, 09:40 AM

I have also noticed these new chips. Design looks impressive, but I don't think any application could use such raw processing power. If they do, ARM would be a better choice IMHO.

hjames · 4th September 2006, 03:46 PM

Quote:

Originally Posted by Jay.slovak

I have also noticed these new chips. Design looks impressive, but I don't think any application could use such raw processing power. If they do, ARM would be a better choice IMHO.

I agree - at present it's a solution in search of a problem, but the general concept is really appealing.

So far the only "killer" apps I can think of are:

decoding/synchronizing noisy/encoded serial transmissions over RF or other lossy channels
high speed "serial" interfaces - i.e. video
low jitter/latency audio - essentially implementing DMA in software
essentially anything involving high speed asynchronous signals with strict timing requirements

I think it would be exceptionally neat if there were a handful of these implemented as IO processors attached to a traditional processor.

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2nd September 2006, 04:08 PM	(permalink)
hjames	Did anyone else see the new "Propeller" chip over at parallax? Had me grinning the whole time I was reading through the data sheet. The most notable points: 8 "cogs" (i.e. cores) 80MHz operation (with a /4 - ~20MHz instruction rate unfortunately) 32 bit instructions 512 x32 words instruction/data memory per cog 8K x32 shared memory per chip a rom table with a built in character font(complete with some electronic symbols ?!) Looks like Parallax actually went and built the successor to the SX series of chips. James Last edited by hjames; 2nd September 2006 at 05:11 PM.

2nd September 2006, 06:03 PM	(permalink)
dknguyen	Yeah. I am not sure what the point is of the cogs? Is it for some kind of parallel processing? To make it more convenient?

2nd September 2006, 08:13 PM	(permalink)
hjames	The idea is to have less dedicated peripherals and let each cog be an "intelligent" peripheral. Each cog could probably implement a couple serial channels, spi, rs232, or whatever protocol, or generate a video signal, or just do general processing. This one chip could probably generate multiple video streams simultaneously... Say you want to create a jitter free RC servo signal - a cog could probably generate a couple servo's worth of signals just sitting there in a tight loop counting clock cycles and doing nothing else. Then for the interface, you have another cog bit-banging the UART and doing all the slow and complex command parsing. This chip is just too different from standard approaches to be "practical" in most applications, but from the hobby perspective, this is a really amazing chip/approach.

2nd September 2006, 08:29 PM	(permalink)
dknguyen	Can you say robot arm?

2nd September 2006, 08:42 PM	(permalink)
hjames	I grabbed one of the eval kits even though I'm pretty sure I won't have enough time to properly dedicate to it. It's just so amazingly close to some of the approaches I wanted to try when I first started using FPGAs. It's the ultimate in distributed processing. Emulating neural nets or having each cog emulate a couple dozen interacting state machines would be so easy to try out on this thing. Throw a couple chips together and you can have as many interacting behaviours and control inputs/outputs as you would ever want. Unfortunately the chips are really expensive, but if they drop the price a bit, I can imagine a board with a handful of these chips along with some CPLDs to route signals between chips... wow. Can you say "sea of processors"?

3rd September 2006, 07:51 AM	(permalink)
Someone Electro	You can still take multiple MCUs and link them togetter by I2C or SPI __________________ Il give you shocking experience.

3rd September 2006, 11:12 AM	(permalink)
hjames	The trick here is that the cogs are all implemented in ram - a single 512 word memory holds all the program and data code. Self modifying code and runtime code uploads/downloads would be the new tricks you can use with this chip. Essentially it would be possible to reallocate processor resources when you need them - or time multiplex them if it's fast enough.

4th September 2006, 09:40 AM	(permalink)
Jay.slovak	I have also noticed these new chips. Design looks impressive, but I don't think any application could use such raw processing power. If they do, ARM would be a better choice IMHO. __________________ "I share, thus I am" Jay.slovak Read this! ICD2 Clone Best PIC/DsPIC Bootloader Read my Inchworm ICD2 review!