Dynamic Partial Reconfigurability
Now a days FPGA’s have become the number one choice for any Hardware Developer when it comes to ASIC design or Future proof design . Over the last 12 years FPGA’s have grown to mind boggling proportions in the number of gates per FPGA and the variety of ip-blocks avialble . They have in fact overlapped some the functionality of an ASIC/ASSP and in some areas surpassed their performance.
One the most outstanding features of FPGA’s that have given them the edge over ASIC/ASSP is their full cum partial dynamic reconfigurability. I have drawn a concept of how to use an Altera Cyclone-ll FPGA to implement a multiple of DSP Filter blocks as they are required or as the monitoring engine sees fit. In this scheme its a 32-bit Nios-ll processor as a monitoring engine, which is provided by Altera in their FPGA IDE Quartus-ll. In this layout Nios-ll acts a supervisor/controller, while the rest of the silicon is left for DSP Blocks to be implemented. ...

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