Note: I am not finished with this article yet. I used to have admin permissions to save without publishing as well as publishing when I was finished with the article. My permissions seem to have been changed when the new ETO website came online.
If EM or any of the mods and reset my permissions as described above that would be excellent.
Most of you who use the PIC microcontrollers have probably noticed that while they have on-chip data EEPROM, most are limited to around 256B. Some of the more advanced 18F series have 1KB. However, some projects simply require more non-volatile memory for storage of critical data. If your project calls for a GLCD, having a large amount of data EEPROM is a must for storing bit-map images that will be displayed on the LCD display.
With the availability of serial EEPROM chips, we can interface one to a PIC with just 2-3 pins. Microchip has the 24LCxxx series of EEPROMs with sizes ranging all the way up to 128KB and they work via an I2C interface. In this article, we will cover interfacing a PIC16F887 to a 24LC64 EEPROM, as well as how to write up code to make it work.
The code used in this article will be PIC assembly code. We will first cover the hardware interface, then we will cover the software.
Hardware Interace
I2C stands for "Inter-Integrated Circuit". It is a synchronous serial protocol used to allow integrated circuits to communicate with each other over a 2-wire bus. I2C supports multiple master devices as well as multiple slave devices on the same bus. Master and slave devices can both transmit as well as receive, but only the master can send the clock signal as well as transmit addresses and commands to the slave devices.
One bus line is the SCL line. This line carries the synchronous clock signal from the master devices to the slave devices on the bus. The other bus line is the SDA line. This line carries bidirectional data between master and slave devices.
While both master and slave can receive and transmit, they can only do so in half-duplex fashion. This means that only two devices can communicate simultaneously (one master and one slave), but the master device cannot transmit at the same time that the slave is transmitting and vice-versa. Only two modes are available on the I2C bus -
* Master Transmit/Slave Receive
* Slave Transmit/Master Receive
While the slave device can transmit, it can only transmit when the master device tells it to do so. Everything that occurs on the I2C bus is via direct control from the master device. If the slave is transmitting, this means that the master is requesting data from the slave. If the slave is receiving, this means that the master is sending data to the slave.
The I2C bus idles in a high state. For each I2C event, the master device first asserts control of the bus by sending a start bit to the slave. It does this by first pulling the SDA line low, then follows by pulling the SCL line low. The master device now has control of the I2C bus.
If a master device on the bus attempts to assert control of the bus while another master device has control, this results in a data collision error. In software, it makes sense to have each master device test the bus to see if the bus is free, then assert control of the bus to prevent this condition from occurring.
If EM or any of the mods and reset my permissions as described above that would be excellent.
Most of you who use the PIC microcontrollers have probably noticed that while they have on-chip data EEPROM, most are limited to around 256B. Some of the more advanced 18F series have 1KB. However, some projects simply require more non-volatile memory for storage of critical data. If your project calls for a GLCD, having a large amount of data EEPROM is a must for storing bit-map images that will be displayed on the LCD display.
With the availability of serial EEPROM chips, we can interface one to a PIC with just 2-3 pins. Microchip has the 24LCxxx series of EEPROMs with sizes ranging all the way up to 128KB and they work via an I2C interface. In this article, we will cover interfacing a PIC16F887 to a 24LC64 EEPROM, as well as how to write up code to make it work.
The code used in this article will be PIC assembly code. We will first cover the hardware interface, then we will cover the software.
Hardware Interace
I2C stands for "Inter-Integrated Circuit". It is a synchronous serial protocol used to allow integrated circuits to communicate with each other over a 2-wire bus. I2C supports multiple master devices as well as multiple slave devices on the same bus. Master and slave devices can both transmit as well as receive, but only the master can send the clock signal as well as transmit addresses and commands to the slave devices.
One bus line is the SCL line. This line carries the synchronous clock signal from the master devices to the slave devices on the bus. The other bus line is the SDA line. This line carries bidirectional data between master and slave devices.
While both master and slave can receive and transmit, they can only do so in half-duplex fashion. This means that only two devices can communicate simultaneously (one master and one slave), but the master device cannot transmit at the same time that the slave is transmitting and vice-versa. Only two modes are available on the I2C bus -
* Master Transmit/Slave Receive
* Slave Transmit/Master Receive
While the slave device can transmit, it can only transmit when the master device tells it to do so. Everything that occurs on the I2C bus is via direct control from the master device. If the slave is transmitting, this means that the master is requesting data from the slave. If the slave is receiving, this means that the master is sending data to the slave.
The I2C bus idles in a high state. For each I2C event, the master device first asserts control of the bus by sending a start bit to the slave. It does this by first pulling the SDA line low, then follows by pulling the SCL line low. The master device now has control of the I2C bus.
If a master device on the bus attempts to assert control of the bus while another master device has control, this results in a data collision error. In software, it makes sense to have each master device test the bus to see if the bus is free, then assert control of the bus to prevent this condition from occurring.
