micpic

Hi,

I want to design a circuit that converts LCD signal to TV signal, but I have no idea . My problem is for example, I have LCD signal (24 bits) with 2 synchro signal(horizontal+vertical) 1024x700 pixels, signals are not entrelaced, and I want to visualize on TV (for example NTSC system).

If anyone have some idea of bloc schematic, components to use!

thanks!

Nigel Goodwin

Well your request doesn't make much sense?, but whatever it actually is, you looking at standards conversion - which is complicated and expensive.

Essentially you write into memory, and read out at a different speed, but also have to scale the image to make it fit. It's FAR from a simple process!.

__________________
PIC programmer software, and PIC Tutorials at:
http://www.winpicprog.co.uk

micpic

Thanks for your answer guy!

For the design, my problem is to change non enterlaced signal to enterlaced signal. To converts enterlaced signal to PAL signal video, I'm thinking to use AD725 component.

if i understand , i must write data in memory(even+ odd) and read even during first vertical synchro and after odd during the second vertical synchro?

Thanks!

HarveyH42

http://www.epanorama.net/links/videochips.html

Bunch of related links, maybe something will work...

micpic

Hi Harvey!

Thanks for your answer and also for links! i will try to read datasheets for components and to try to mount bloc schematic . So, if you have ideas or advices of this project, I'm thankful.

Thanks!

HarveyH42

Back when I still played video games. Thought it would cool to put them on the projection TV. Seemed pretty complicated to build, and chips were expensive and impossiable to find. There are ready-made units in the $100 range these days, but I haven't played computer games in years, still have the same TV though.

micpic

Ok!

It' s right, but i want just to try to design this project without buying chips, just for my curiosity, i want to elaborate schematic blocs, specifications, detail of every bloc.

Have you a schematic bloc for this project?

yngndrw

Well I can tell you how I'd do it - But I don't know the differences between PAL and NTSC, so this is for PAL.

If the frequencys are different, I'd use three memory sections. The first would store the input signal and would be updated as the input signal changes. I would then have an output memory section which would store the data to be displayed. Finally I would have a middle memory section which would convert the frequency.

Once the first memory section is full, if the middle memory section is not being used the first memory would be copied into the second. Once the output signal has finished its vertical sync, if the middle memory wasn't being written to the middle memory would be copied into the third memory.

The third memory will be continually read an output to the screen in the correct format. This will also allow for changes in size.

Each memory section would consist of two RAM chips each of which would be large enough to store half of the input screen size. In the input stage, even lines are written to one RAM chip and odd ones are written to the other. In the output stage the even chip would be sequentially read followed by the output chip. This allows interlacing.

Hope that helps.

micpic

Hi!
thanks for reply, so, could you send me schematic bloc?

thanks

ronsimpson

No one is going to send a schematic. This is a BIG project.
I have designed several NTSC/PAL to LCD converters and the like. I would not start this unless I had nothing to do from now to Christmas.
This is as complicated as the video board in your PC.
Open up your LCD monitor. This is more complicated than that.

yngndrw

If you need someone to make the schmatic for you then the project is too complex for you i'm afraid. Anyway I don't have a schematic, I designed that off the top of my head. (Hence it's probably got quite a few bugs / things that should be done differently !)

Just out of interest ronsimpson, how would you do the same project in terms of the design ? Is there a better way that what I suggested ?

micpic

ok!

for this design, i know it exists in the market, but i want to design it in a paper and to understand the functionnaly. I think about BU1425AK component, but as signal inputs are not enterlaced, i don't know how to do.

In fact, for example i have signals about module compulab CM-X270W (LCD signal) (http://www.compulab.co.il) and i want to display these in my TV.

here is the synoptic of schema in which i want to do:

[24 bits=> R:8bits,G:8bits,B:8bits + sync signals] -> [component? + memory?] -> [R,G,B + sync signals] -> [component?] -> TV signal

can you suggest me?

ronsimpson

Yngndrw, You wanted to know how I would do this.

Lets say we are going to convert DVI video at 1024x700 to NTSC video.

Convert serial video data (DVI) to TTL 24 bit parallel video.
http://www.siliconimage.com/docs/SiI-DS-0096.pdf

In a FPGA we will do the video scaling and interlacing.

>Here is a method to convert non-interlaced to interlaced using only 1024x24 bit of video memory.
First frame: scan in only the odd lines of video. (1,3,5,7….) Disregard the even lines.
Line 1 is scanned into memory at the fast rate while it is scanned back out at ½ speed.
Second frame: scan in the even lines (2,4,6,….) while disregarding the odd lines.
Line 2 is scanned into memory at full speed while it is scanned back out at ½ speed.

>If the video source has a 60hz refresh rate then the video conversion can be done with very little RAM. The video in and video out use the same 60hz video sync. We need to convert 700 video lines to 486 video lines. This is done by storing only 4 lines of video in memory. (1024 x 4 x 24) Example: While line 50 is being scanned into memory we have lines 49, 48 and 47 to process to make one line of NTSC video.

>The NTSC pixel is lager than the LCD pixel. For this moment in time lets say it overlaps all of pixel 48.7 (line 48, pixel 7) and parts of the surrounding pixels. Or to say it another way: (50% of line 49, 100% of line 48 and 10% of line 47) and (5% of pixel 6, 100% of pixel 7 and 55% of pixel 8)

We need a math engine that looks at 9 pixels at one time. For an example at a moment in time it is looking at line 49, 48 and 47 while looking at pixel 6, 7 and 8.

49.6, 49.7, 49.8
48.6, 48.7, 48.8
47.6, 47.7, 47.8

NTSC pixel RED = (49.6*2.5%+49.7+50%+49.8+27.5%)+
(48.6*5%+48.7*100%+48.8*55%)+
(47.6*0.5%+47.7*10%+47.8*5.5%)
We need to do this again for Green and Blue. Then probably convert to Y, U and V at 14.31818 million times a second.

>If the video source is anything other than 60hz then we must store one page of video. We need 1024 x 700 x 24 bit memory. The video is scanned into memory at the DVI speed. The video is scanned out of memory at NTSC speed.

Convert to analog NTSC
AVD7120 Convert parallel TTL video to analog RGB.
AD724 converts RGB analog video to NTSC.

yngndrw

Wow, there's the difference between someone who doesn't know about video (Me) and someone who knows a lot about it (You), thanks for taking the time to go through that - It definatly shows the size of the project.

A lot of parallel processing aswell.

micpic

Ok thanks!

In fact, if i understand you use fpga to separate even and odd frame, and two memory like SRAM to store these frame, and an another fpga to create the two synchro for TV signal, and finally you use AD724 to convert analog RGB to PAL?